• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.221-224
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• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.438-445
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• 2017

This paper presents a low-power high-resolution band-pass ${\Sigma}{\Delta}$ ADC for accelerometer applications. The proposed band-pass ${\Sigma}{\Delta}$ ADC consists of a high-performance 6-th order feed-forward ${\Sigma}{\Delta}$ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of $5mm^2$. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.

• Journal of The Korean Society of Agricultural Engineers
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• v.52 no.2
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• pp.43-50
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• 2010

This study was carried out to evaluate the vertical stress properties in sandy soil according to changes of foundation condition in soil bin compacted three layers. The following conclusions and comparisons have been made based on careful analysis from theoretical and experimental methods. : When sandy soil subjected to circular uniform load, the vertical stress increments ($\Delta\sigma_z$) was increased as load increasing, the maximum values of $\Delta\sigma_z$ was achieved at the point loading axis, and $\Delta\sigma_z$ was not shown over at a distance of three times of loading plate width (B). The vertical stress increments were achieved largely at 80 % relative compaction (Rc) compared to 95 % relative compaction due to stress concentration in sandy soil. When sandy soil subjected to circular uniform load, the $\Delta\sigma_z$ differences between theoretical and experimental values as load increased were more increased and its maximum differences were achieved at stress axis. When gravel surface macadamized over sandy soil subjected to load, the $\Delta\sigma_z$ was concentrated to load axis as load increasing, so that macadamization will be decreased load transmission.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.4
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• pp.1-8
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• 2010

In this paper, we propose a new gain optimization technique for Sigma-Delta A/D converters. In the proposed scheme, multiple gain set candidates showing maximum SNR in the modulator block are selected, and then multiple gain set candidates are investigated for minimum MSE in decimation block. Through CIC decimation filter simulation, it is shown that second SNR ranking candidate in modulation block is the best gain set.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.1
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• pp.54-61
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• 2009

This paper proposes the 2nd-order SDSDM (Space Dithered Sigma-Delta Modulation) for performance improvement of a buck converter. The PWM (Pulse Width Modulation) has a drawback in that power spectrum tends to be concentrated around the switching frequency. The resulting harmonic spikes cause a EMI(Electromagnetic Interference) and switching loss in semiconductor, etc. The 1st-order SDSDM scheme is a kind of DSDM for reducing these harmonic spikes. In this scheme, a switching frequency is spread through random dither generator placed on input part. In experimental result, the proposed 2nd-order SDSDM is confirmed by applying to a buck converter.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1701-1705
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• 2004

This paper presents a design and analysis of electromechanical sigma-delta modulator for MEMS gyroscope, which enables us to control the proof mass and to obtain an exact digital output without additional A/D conversion. The system structure and the circuit realization of the sigma-delta modulation are simpler than those of the analog sensing and feedback circuit. Based on the electrical sigma-delta modulator theory, a compensator is designed to improve the closed loop resolution of the sensor. With the designed compensator, we could obtain enhanced closed-loop performances of the gyroscope such as larger bandwidth, lower noise, and digital output comparing with the results of analog open-loop system.