• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.4
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• pp.359-367
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• 2023

In order to ensure the high-integrity of reference stations of satellite navigation system, cycle slip should be precisely monitored and compensated. In this paper, we proposed a cycle slip algorithm for the integrity monitoring of the reference stations. Unlike the legacy method using the Melbourne-Wübbena (MW) combination and ionosphere combination, the proposed algorithm is based on ionosphere combination only, which uses high precision carrier phase observations without pseudorange observations. Two independent and complementary ionosphere combinations, Ionospheric Negative (IN) and Ionospheric Positive (IP), were adopted to avoid insensitive cycle slip pairs. In addition, a second-order time difference was applied to the IN and IP combinations to minimize the influence of ionospheric and tropospheric delay even under severe atmosphere conditions. Then, the cycle slip was detected by the thresholds determined based on error propagation rules, and the cycle slip was identified through weighted least square method. The performance of the proposed cycle slip algorithm was validated with the 1 Hz dual-frequency carrier phase data collected under the difference levels of ionospheric activities. For this experiment, 15 insensitive cycle slip pairs were intentionally inserted into the raw carrier phase observations, which is difficult to be detected with the traditional cycle slip approach. The results indicate that the proposed approach can successfully detect and compensate all of the inserted cycle slip pairs regardless of ionospheric activity. As a consequence, the proposed cycle slip algorithm is confirmed to be suitable for the reference station where real time high-integrity monitoring is crucial.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.57-64
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• 2004

In this paper, we propose a RZ/HRZ mixture data transmission method for the asynchronous circuit design to reduce Power consumption. The dual-rail data with Rf decoding scheme is used to design asynchronous circuit, and it is easy to get a completion signal of the data validity from the native data as contrasted with sin91e-rail. However, the dual-rail scheme suffers from large chip area and increasing of Power consumption from all signals by the switching of the return-to-zero. We need to diminish number of circuit switching. The proposed RZ/HRZ data transmission reduces a switching activity to about 50% and it shows 23% lower power consumption than the conventional dual-rail coding with RZ's.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.716-720
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• 2006

In this paper, we designed and proposed new routing algorithm that can support a variety of vital-sign traffic characteristic and could be applicable to USN for telemedicine by using adaptive transmission power level and increase frequency of routing request message. In proposed routing algorithm, when an emergency vital-sign traffic is applied, we use large transmission power to reduce route query response time and make the priority order in route process. On the other hand, for non emergency vital-sign traffic, we use low transmission power and adaptive decrease frequency of routing request message. which is insensitive to delay. The proposed scheme should be better QoS performance in complex USN than conventional method, which is performed based on uniform transmission power level.

• Proceedings of the KOSOMBE Conference
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• v.1994 no.12
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• pp.113-116
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• 1994

Estimation of the evoked potential using the iterated bispectrum and cross-correlation (IBC) has been tried for both simulation and real clinical data. Conventional time average (TA) method suffers from synchronization error when the latency time of the evoked potential is random, which results in poor SNR distortion in the estimation of EP waveform. Instead of EP signal average in time domain, bispectrum is used which is insensitive to time delay. The EP signal is recovered by the inverse transform of the Fourier amplitude and phase obtained from the bispectrum. The distribution of the latency time is calculated using cross-correlation between EP signal estimated by the bispectrum and the acquired signal. For the simulation. EEG noise was added to the known EP signal and the EP signal was estimated by both the conventional technique and bispectrum technique. The proposed bispectrum technique estimates EP signal more accurately than the conventional technique with respect to the maximum amplitude of a signal, full width at half maximum(FWHM). signal-to-noise-ratio, and the position of maximum peak. When applied to the real visual evoked potential(VEP) signal. bispectrum technique was able to estimate EP signal more distinctively. The distribution of the latency time may play an important role in medical diagonosis.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.