5.8 GHz PLL using High-Speed Ring Oscillator for WLAN

WLAN을 위한 고속 링 발진기를 이용한 5.8 GHz PLL

  • 김경모 (삼성전자(주) 메모리사업부) ;
  • 최재형 (동국대학교 전자공학과) ;
  • 김삼동 (동국대학교 전자공학과) ;
  • 황인석 (동국대학교 전자공학과)
  • Published : 2008.03.25

Abstract

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

본 논문에서는 고속 링 발진기를 이용한 WLAN용 5.8 GHz PLL을 제안하였다. 제안한 PLL에 사용된 링 발진기는 부 스큐 지연방식을 이용하여 차동 구조로 설계되었다. 따라서 Power-Supply-Injected Noise에 둔감하며, 1/f Noise를 감소시키기 위하여 Tail Current Source를 사용하지 않았다. 제안한 링 발진기는 $0{\sim}1.8V$의 컨트롤 전압에 걸쳐 $5.13{\sim}7.04GHz$의 발진주파수를 보였다. 본 논문에서 제안한 PLL 회로는 0.18 um 1.8 V TSMC CMOS 라이브러리를 기본으로 하여 설계하였고 시뮬레이션을 통하여 성능을 검증하였다. 동작 주파수는 5.8 GHz이며, Locking Time은 2.5 us, 5.8 GHz에서의 소비 전력은 59.9mW로 측정되었다.

Keywords

References

  1. 이승훈, 김범섭, 송민규, 최중호, CMOS 아날로그/혼성모드 집적시스템 설계, 시그마 프레스, 1999
  2. J. H. C. Zhan, J.S. Duster and K. T. Kornegay, "Analysis of Emitter Degenerated LC Oscillators Using Bipolar Technologies," IEEE Symp. Circuits and Systems 2003, pp. 669-672
  3. T. K. K. Tsang and M. N. El-Gamal, "A High Fiqure of Merit and Area-Efficient Low-Voltage(0.7-1V) 12GHz CMOS VCO," 2003 IEEE RFIC Symp, Dig., pp. 89-92, Jun. 2003
  4. C. Hung, L. Shi, I. Laguado, and K. K. O, "A 25.9GHz Voltage-Controlled Oscillator Fabricatied in a CMOS Process," IEEE Symp. on VLSI Circuits, pp. 100-101, 2000
  5. M. Tiebout, H. Wohlmuth, an W. Simburger, "A 1 V 51 GHz Fully-Integrated VCO in 0.12 um CMOS," ISSCC Dig. of Tech. Papers, pp. 300-301, 2002
  6. In-Chul Hwang, Chulwoo Kim. and Sung-mo Kang, "A CMOS Self-Regulating VCO with low supplys sensitivity," IEEE Journal of Solid-State Circuits, Vol, 39, issue 1, pp. 42-48, Jan. 2004 https://doi.org/10.1109/JSSC.2003.820881
  7. Kuo-Hsing Cheng, Ching-Wen Lai and Yu-Lung Lo, "A CMOS VCO for 1V, 1GHz PLL Applications," 2004 IEEE Asian-Pacific Conference on Advanced System Integrated Circuits, pp. 150-153, Aug. 2004
  8. Joonsuk Lee, Beomsup Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE Journal of Solid-State Circuits, Vol, 35, issue 8, pp. 1137-1145, Aug. 2000 https://doi.org/10.1109/4.859502
  9. Chan-Hong Park, Beomsup Kim, "A low-noise, 900-MHz VCO in 0.6um CMOS," IEEE Journal of Solid-State Circuits, Vol. 34, issue 5, pp. 586-591, May 1999 https://doi.org/10.1109/4.760367
  10. Seong-Jun Lee, Beomsup Kim, Kwyro Lee, "A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme," IEEE Journal of Solid-State Circuits, Vol, 33, issue 2, pp. 289-291, Feb. 1997
  11. 김성하, 김삼동, 황인석, "향상된 부 스큐 고속 VCO를 이용한 초고주파 PLL," 전자공학회 논문지 제 42 권 SC편 제 6 호, pp. 23-36, Nov. 2005