• Clinical Psychopharmacology and Neuroscience
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• 제16권4호
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• pp.489-493
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• 2018

Objective: This study was to identify whether working memory (WM) can be clearly subdivided according to auditory and visual modality. To do this, we administered the most recent and universal clinical WM measures in a mixed psychiatric sample. Methods: A total of 115 patients were diagnosed on the basis of DSM-IV diagnostic criteria and with MINI-Plus 5.0, a structured diagnostic interview. WM subtests of Korean version of Wechsler Adult Intelligence Scale-IV and Korean version of Wechsler Memory Scale-IV were administered to assess WM. Confirmatory factor analysis (CFA) was used to observe whether WM measures fit better to a one-factor or two-factor model. Results: CFA results demonstrated that a two factor model fits the data better than one-factor model as expected. Conclusion: Our study supports a modality model of WM, or the existence of modality-specific WM systems, and thus poses a clinical significance of assessing both auditory and visual WM tests.

• 한국어학
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• 제79권
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• pp.91-116
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• 2018

This paper aims at proposing issues of breath and memory in speech based on the quantitative analysis of breath groups and pause units in Korean. As a human being, we have two kinds of limitations on continuing speech; breath and memory. The prosodic structure and temporal structure of spontaneous speech data from six speakers were closely examined. One of the main findings of the present study is that the prosodic structure and temporal structure of Korean appears to reflect the breath and memory problems in speech.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• 정보저장시스템학회논문집
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• 제3권2호
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• pp.94-112
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• 2007

Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/$inch^2$ and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50nm was 16.9 years at $80^{\circ}C$. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than $1\times10^{-4}$ was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/$inch^2$.

• 전자공학회논문지
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• 제52권5호
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• pp.66-73
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• 2015

OFDM 기반 통신시스템에서 IFFT는 중요한 핵심 컴포넌트 중의 하나이다. 본 논문에서는 OFDM 기반 통신시스템을 위한 메모리가 효율적인 새로운 IFFT 설계 방법을 제안한다. OFDM 기반 통신시스템에서 사용되는 IFFT의 입력신호는 데이터 변조신호, 파일럿과 널(null) 신호로 구성된다. 제안한 방법은 IFFT 입력신호의 매핑을 통해 IFFT에서 가장 큰 메모리를 차지하는 비트리버스의 메모리를 감소시키는 데 초점을 둔다. 비트리버스의 메모리 크기를 감소시키기 위해 DIT기반 구조에 적합한 선택 매핑기법을 제안한다. 시뮬레이션을 통해 제안한 방법이 기존 방법과 비교하여 약 50%의 메모리가 감소됨을 보인다.

• 전기학회논문지
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• 제59권6호
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• 한국멀티미디어학회논문지
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• 제12권2호
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• pp.165-177
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• 2009

센서노드(sensor node)에서의 데이터 기록을 위해 NAND 플래시 메모리 기반의 임베디드 데이터베이스 시스템이 널리 사용되고 이다. 플래시 메모리의 쓰기 및 삭제연산은 읽기 연산에 비해 시간이 많이 소모되고 기억 소자를 마모시킨다. 따라서 이러한 연산들을 줄이는 것은 데이터베이스 시스템의 성능 향상과 메모리의 수명 증대 측면에서 중요하다. 본 논문에서는 이를 위해 지연쓰기 기법을 제안한다. 이 기법은 데이터페이스 페이지의 갱신 영역을 별도의 지연쓰기 레코드로 저장하여 데이터베이스 페이지 쓰기를 줄임으로써 플래시 메모리에 대한 쓰기연산과 삭제 연산을 감소시킨다. 따라서 제안하는 기법은 데이터 기록의 비중이 높은 센서노드 데이터베이스 시스템의 성능을 높이고 플래시 메모리의 수명을 늘리게 된다.

• 전기전자학회논문지
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• 제4권2호
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• pp.212-224
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• 2000

본 논문에서는 영상 응용프로그램의 처리 속도를 향상하기 위한 병렬처리 시스템을 제안한다. 병렬처리 시스템은 Pipelined SIMD 구조를 갖고 있으며, 다수개의 처리기와 다중접근 기억장치로 구성된다. 다중접근 기억장치는 메모리 모듈들과 메모리 제어부로 구성되며, 메모리 제어부는 메모리 모듈 선택 모듈, 데이터 라우팅 모듈, 그리고 주소 계산 및 라우팅 모듈로 구성되어 있으며, 블록, 행, 그리고 열 내의 데이터를 동시에 접근할 수 있는 기능을 제공한다. 제안한 병렬처리 시스템을 검증하기 위해서 형태학적 필터를 적용하여 기능 검증 및 처리속도를 확인하였다.

• 대한임베디드공학회논문지
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• 제8권5호
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• pp.235-242
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• 2013

Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.

• International journal of advanced smart convergence
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• 제8권1호
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.