Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Pipelined Parallel Processing System for Image Processing

영상처리를 위한 Pipelined 병렬처리 시스템

  • Lee, Hyung (Department of Computer Engineering, Chongnam National University) ;
  • Kim, Jong-Bae (WOOKSUNG Electronics, Inc.) ;
  • Choi, Sung-Hyk (Department of Computer Engineering, Chongnam National University) ;
  • Park, Jong-Won (Department of Information Communications Engineering, Chungnam National University)
  • 이형 (충남대학교 컴퓨터공학과) ;
  • 김종배 (욱성전자) ;
  • 최성혁 (충남대학교 컴퓨터공학과) ;
  • 박종원 (충남대학교 정보통신공학과)
  • Published : 2000.12.01
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Abstract

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

본 논문에서는 영상 응용프로그램의 처리 속도를 향상하기 위한 병렬처리 시스템을 제안한다. 병렬처리 시스템은 Pipelined SIMD 구조를 갖고 있으며, 다수개의 처리기와 다중접근 기억장치로 구성된다. 다중접근 기억장치는 메모리 모듈들과 메모리 제어부로 구성되며, 메모리 제어부는 메모리 모듈 선택 모듈, 데이터 라우팅 모듈, 그리고 주소 계산 및 라우팅 모듈로 구성되어 있으며, 블록, 행, 그리고 열 내의 데이터를 동시에 접근할 수 있는 기능을 제공한다. 제안한 병렬처리 시스템을 검증하기 위해서 형태학적 필터를 적용하여 기능 검증 및 처리속도를 확인하였다.

Keywords

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