• Title/Summary/Keyword: DLL

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Effect of Ribcage Stabilization Using a Belt on EMG Activity of the Abdominal Muscles During Double Leg Lowering in the Supine Position (벨트를 이용한 가슴우리 고정이 누운자세에서 다리내리기 동안 복부 근육들의 근활성도에 미치는 영향)

  • Weon, Jonghyuck
    • Journal of The Korean Society of Integrative Medicine
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    • v.5 no.2
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    • pp.25-32
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    • 2017
  • Purpose : The purpose of this study was to determine the effect of ribcage stabilization using a belt in the supine position during double leg lowering (DLL) by investigating the electromyographic (EMG) activities of the abdominal muscles. Methods : Twenty-two subjects with lumbar extension syndrome were recruited. EMG activity was recorded from rectus abdominalis (RA) and internal oblique abdominalis (IO), external oblique abdominalis (EO) muscles while subjects performed three double leg lowering exercises: double leg lowering (DLL), double leg lowering with abdominal draw-in maneuver (DLL-ADIM), and double leg lowering with ribcage stabilization using a belt (DLL-belt). RA, IO, and EO EMG activity were analyzed via one-way repeated-measures analysis of variance (ANOVA). Bonferroni correction was performed where significant differences were identified (p<.017, .05/3). Results : RA, IO, and EO EMG activity differed significantly among the three exercises (p<.05). The use of post hoc pair-wise comparison with Bonferroni correction showed that RA muscle activity significantly differed among the three exercises (p<.017), and IO muscle activity in the DLL exercise was significantly decreased compared to the DLL-ADIM and DLL-belt exercises (p<.017). There was no significant difference between IO muscle activity for DLL-ADIM and DLL-belt exercises (p>.017). EO muscle activity in the DLL-belt exercise was significantly increased compared to both DLL and DLL-ADIM exercises (p<.017), but there was no significant difference between EO muscle activity for DLL and DLL-ADIM exercises (p>.017). Conclusion : DLL-belt is a more effective exercise for activating the abdominal muscles than DLL-ADIM exercise. Therefore, we recommend DLL-belt exercises for strengthening the abdominal muscles.

Wide Range Analog Dual-Loop Delay-Locked Loop (광대역 아날로그 이중 루프 Delay-Locked Loop)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.74-84
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    • 2007
  • This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

2-Stage Mixed-Mode Delay Locked Loop with Low Jitter (작은 지터를 가지는 2단 구조의 혼성모드 DLL)

  • Kim, Dae-Hee;Hwang, In-Seok
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.963-964
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    • 2006
  • By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

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Study on the API Hooking Method Based on the Windows (윈도우 API 후킹 탐지 방법에 대한 연구)

  • Kim, Wan-Kyung;Soh, Woo-Young;Sung, Kyung
    • Journal of Advanced Navigation Technology
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    • v.13 no.6
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    • pp.884-893
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    • 2009
  • Recently, malicious attacks for Windows operate through Window API hooking in the Windows Kernel. This paper presents the API hooking attack and protection techniques based on Windows kernel. Also this paper develops a detection tool for Windows API hooking that enables to detect dll files which are operated in the kernel. Proposed tool can detect behaviors that imports from dll files or exports to dll files such as kernel32.dll, snmpapi.dll, ntdll.dll and advapidll.dll, etc.. Test results show that the tool can check name, location, and behavior of API in testing system.

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A DLL-Based Frequency Synthesizer for Generation of Various Clocks (가변 클록 발생을 위한 DLL 주파수 합성기)

  • 이지현;송윤귀;최영식;최혁환;류지구
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1153-1157
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    • 2004
  • This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

Implementation and Performance Evaluation of the Vector DLL in a Software GPS Receiver (소프트웨어 GPS 수신기에서의 벡터 DLL 구현과 성능 분석)

  • Lim, Deok-Won;Kim, Jeong-Won;Jeong, Ho-Cheol;Hwang, Dong-Hwan;Lee, Sang-Jeong
    • Proceedings of the KIEE Conference
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    • 2008.04a
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    • pp.65-66
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    • 2008
  • A vector DLL represents signal tracking scheme utilizing navigation results, and it has been known that it has better performance than a conventional scalar DLL. This paper discusses the structure and conceptual benefits of the vector DLL, and describes implementation of the vector DLL in a software GPS receive. Also, the benefits of the vector DLL are confirmed by an experiment. Through the experiment, the code tracking accuracy between the vector DLL and a scalar DLL implementation is compared in static environments, and the navigation accuracy is analyzed using GPS signals received from a commercial GPS simulator.

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Performance Analysis of Extended n-$\Delta$ Dely-Lock Loops (n-$\Delta$ Delay-Lock Loops의 성능 해석)

  • Ryu, Seung-Mun;Eun, Jung-Gwan;Kim, Jae-Gyun
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.18 no.1
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    • pp.16-24
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    • 1981
  • The delay-lock loop (DLL) is a statistically optimum device for tracking the de]ay difference between two correlated waveforms. In this paper an extended n - $\Delta$ (n=1,2,3‥‥) DLL is described, and its baseband performance including the frequency to lose lock is analyzed. The present DLL system employs a correlator and a pseudonoise sequence synthesizer that has been improved from the previously used ones The shape of the correlator characterigtic has the form of expanded S-curve. Despite of increase noise, this extended DLL has desirable characteristics in tracking range and initial synchronization time. Comparing a 3 - $\Delta$ DLL with a 1 - A DLL, the former Bives three times faster initial synchronization time with the serial synchronization method, and gives two times immunity against doppler shift.

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LDB2 regulates the expression of DLL4 through the formation of oligomeric complexes in endothelial cells

  • Choi, Hyun-Jung;Rho, Seung-Sik;Choi, Dong-Hoon;Kwon, Young-Guen
    • BMB Reports
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    • v.51 no.1
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    • pp.21-26
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    • 2018
  • Delta-like ligand 4 (DLL4) expression in endothelial cells is intimately associated with angiogenic sprouting and vascular remodeling, but the precise mechanism of transcriptional regulation of DLL4 remains incompletely understood. Here, we showed that LIM-domain binding protein 2 (LDB2) plays an important role in regulating basal DLL4 and VEGF-induced DLL4 expression. Knockdown of LDB2 using siRNA enhanced endothelial sprouting and tubular network formation in vitro. Injection of ldb2-morpholino resulted in defective development of intersegmental vessels in zebrafish. Reduction or over-expression of LDB2 in endothelial cells decreased or increased DLL4 expression. LDB2 regulated DLL4 promoter activity by binding to its promoter region and the same promoter region was occupied and regulated by the LMO2/TAL1/GATA2 complex. Interestingly, LDB2 also mediated VEGF-induced DLL4 expression in endothelial cells. The regulation of DLL4 by the LDB2 complex provides a novel mechanism of DLL4 transcriptional control that may be exploited to develop therapeutics for aberrant vascular remodeling.

Memory Injection Technique and Injected DLL Analysis Technique in Windows Environment (윈도우 환경에서의 메모리 인젝션 기술과 인젝션 된 DLL 분석 기술)

  • Hwang, Hyun-Uk;Chae, Jong-Ho;Yun, Young-Tae
    • Convergence Security Journal
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    • v.6 no.3
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    • pp.59-67
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    • 2006
  • Recently the Personal Computer hacking and game hacking for the purpose of gaining an economic profit is increased in Windows system. Malicious code often uses methods which inject dll or code into memory in target process for using covert channel for communicating among them, bypassing secure products like personal firewalls and obtaining sensitive information in system. This paper analyzes the technique for injecting and executing code into memory area in target process. In addition, this analyzes the PE format and IMPORT table for extracting injected dll in running process in affected system and describes a method for extracting and analyzing explicitly loaded dll files related with running process. This technique is useful for finding and analyzing infected processes in affected system.

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An Anti-Boundary Switching Digital Delay-Locked Loop (안티-바운드리 스위칭 디지털 지연고정루프)

  • Yoon, Junsub;Kim, Jongsun
    • Journal of IKEEE
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    • v.21 no.4
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    • pp.416-419
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    • 2017
  • In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.