대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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작은 지터를 가지는 2단 구조의 혼성모드 DLL

2-Stage Mixed-Mode Delay Locked Loop with Low Jitter

  • 김대희 (동국대학교 전자공학과) ;
  • 황인석 (동국대학교 전자공학과)
  • Kim, Dae-Hee (Dept. of Electronics Engineering Dongguk University) ;
  • Hwang, In-Seok (Dept. of Electronics Engineering Dongguk University)
  • 발행 : 2006.06.21
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초록

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

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