• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.3
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• pp.97-103
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• 2008

In this paper, $256{\times}256$ input image is classified into a validity block and an edge block of $8{\times}8$ block for image compression. DCT(Discrete Cosine Transform) is executed only for the DC coefficient that is validity coefficients for a validity block. Predict the position where a quantization coefficient becomes 0 for an edge block, I propose new algorithm to execute DCT in the reduced region. Not only this algorithm that I proposed reduces computational complexity of FDCT(Forward DCT) and IDCT(Inverse DCT) and decreases encoding time and decoding time. I let compressibility increase by accomplishing other stability verticality zigzag scan by the block size that was classified for each block at the time of huffman encoding each. In addition, the algorithm that I suggested reduces Run-Length by accomplishing the level verticality zigzag scan that is good for a classified block characteristic and, I offer the compressibility that improved thereby.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.180-181
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• 2018

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the array of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform).

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.206-208
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• 2014

본 논문에서는 HEVC (High Efficiency Video Coding)의 IDCT (Inverse Discrete Cosine Transform) 모듈을 AVX2 (Advanced Vector Extensions 2) 명령어 셋을 사용하여 고속화하는 방법을 제안한다. 제안하는 방법은 4 개의 $4{\times}4$ 블록을 AVX2 레지스터에 로드 한 후, 동시에 AVX2 명령어 셋을 통해 한 번에 IDCT 를 수행한다. 제안하는 방법은 $4{\times}4$ 블록 단위로 순차적으로 SIMD(Single Instruction Multiple Data) 명령어 셋을 통해 IDCT 를 수행하는 방법에 비해 명령어 단위의 병렬화 성능을 극대화한다. 실험 결과, HEVC 디코더의 $4{\times}4$ IDCT 에 SIMD 명령어 셋을 적용한 경우 기존의 HM-12.1 에 비해 평균 3.35 배 수행 속도를 향상 시킨 반면, 제안하는 방법은 HM12.1에 비해 평균 9.50 배 수행 속도를 향상 시켰다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.127-130
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• 2002

동영상 장면에서 자막은 흔히 중요한 의미 정보를 나타내기 때문에 영상으로부터 자막 영역을 검출하는 것은 동영상에 대한 의미적인 분석 및 색인 등 다양한 범위에서 널리 응용될 수 있다. 본 논문에서는 DCT 기반으로 압축된 영상에서 자막 후보 영역을 검출하기 위한 고속의 방법을 제안한다. 제안하는 방법은 자막 영역에서 나타나는 수평 밝기 값의 교대 패턴을 검출하기 위하여 각 블록 별로 1회의 1-D IDCT 과정을 필요로 한다

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.48-57
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• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.37-39
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• 2001

본 논문은 여러 가지 데이터 압축 표준에서 채택하고 있는 이차원 이산 여현 변환과 그 역 변환 (DCT/IDCT)를 위한 효율적인 비동기식 행렬 벡터 곱셈기를 설계하였다. 본 논문에서 제안되어진 곱셈기는 일반적으로 DCT/IDCT의 입력 데이터가 대부분 zero입력이거나 또는 작은 비트수로 표현 가능하다는 점을 이용하여 저전력 고성능 동작을 구현할 수 있도록 설계하였다. 비동기식 설계 방식을 채택하여 Zero입력일 경우 곱셈과정을 생략하고, 정적 회로에 기초한 특정 계산 완료 인지 방식(Speculative Completion Sensing)와 비트 분할된 곱셈기를 이용하여 입력 비트 슬라이스에 대해 동적으로 회로의 계산부분을 활성화/비활성화를 동작을 할 수 있도록 설계되어졌다.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1823-1826
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• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.38-40
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• 2007

In this paper, we propose a novel architecture, which is based on DCT (Discrete Cosine Transform), for ME (Motion Estimation) and MC (Motion Compensation). The traditional algorithms of ME and MC based on DCT did not suffer the advantage of the coarseness of the 2-dimensional DCT (2-D DCT) coefficients to reduce the operational time. Therefore, we derive a recursion equation for transform-domain ME and MC and design the structure by using highly regular, parallel, and pipeline processing elements. The main difference with others is removing the IDCT block by using to transform domain. Therefore, the performance of our algorithm is more efficient in practical image processing such as DVR (Digital Video Recorder) system. We present the simulation result which is compare with the spatial domain methods. it shows reducing the calculation cost. compression ratio. and peak signal to noise ratio (PSNR).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.