High Speed 2D Discrete Cosine Transform Processor
- Kim, Ji-Eun (School of Electronics, Information & Communications Eng., Chosun Univ.) ;
- Hae Kyung SEONG (Hanyang Women′s College, Department of Computer Science and Information Technology) ;
- Kang Hyeon RHEE (School of Electronics, Information & Communications Eng., Chosun Univ.)
- Published : 2002.07.01
On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.