• Journal of IKEEE
• /
• v.15 no.2
• /
• pp.134-142
• /
• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.411-414
• /
• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• Journal of IKEEE
• /
• v.15 no.4
• /
• pp.319-323
• /
• 2011

In this paper presents a new model of dual-mode synchronous buck converter with dynamic control for mobile applications was proposed. The proposed circuit can operate at 2.5MHz with supply voltage 2.5V to 5V for low ripple and minimum inductor and capacitor size, which is suitable for single-cell lithium-ion battery supply mobile applications. For high efficiency, the proposed circuit adopts synchronous type and dynamic control. The proposed circuit is designed by using the device parameter of TSMC 0.18um BCD process and the performance is evaluated by Cadence spectre. Experimental board level results show the maximum conversion efficiency is 96% at 100mA load current.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.17 no.5
• /
• pp.36-42
• /
• 2003

This paper presents a new current-source PWM inverter based on Buck-boost configuration to interface between photovoltaic system and utility line. Proposed inverter is consisted by two set of buck-boost topology, and the input inductor is designed to be operated on the discontinuous current conduction mode. So high power factor can be achieved without additional input CtUTent controller. As a result, overall system has simple structure, and it can obtain higher ac output rms voltage than the terminal voltage of the photovoltaic system without additional boosting procedure. The operational modes are theoretically analyzed, and then the validity of the proposed system was verified through simulation and experimental results using a prototype.

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.208-215
• /
• 2009

The high efficiency power management IC(PMIC) with DT-CMOS(Dynamic Threshold voltage MOSFET) switching device for portable application is proposed in this paper. Because portable applications need high output voltages and low output voltage, Boost converter and Buck converter are embedded in One-chip. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. Boost converter and Buck converter, are based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 92.1% and 95%, respectively, at 100mA output current. And Step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.4
• /
• pp.98-107
• /
• 2005

Brushless DC motor(BLDCM) can be driven by 120[^{\circ}]$ square wave voltage and use PWM pulse patterns in two-phase feeding scheme to control the speed of the motor. This Paper introduces four PWM modes used BLDCM control system, and analyzes their different influences on the motor performances using a time-stepped voltage source finite element method. To verify the proposed computational method, we built the prototype motor for electrical power steering(EPS) and compared the predicted and the measured back EMF and phase current.

• Proceedings of the KIPE Conference
• /
• 1999.07a
• /
• pp.327-332
• /
• 1999

In this paper, six harmonic injection PWM method for reducing total harmonic distortion in single switch three phase discontinuous conduction mode boost converter is presented. In the proposed method, periodic six harmonic voltage is injected in the control circuit to vary the duty ratio of the converter switch within a line cycle so that the fifth order harmonic of the input current is reduced. Experimental results are verified by converter operating at 400V/6kW with three phase 140V~220V input.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2024-2034
• /
• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of Power Electronics
• /
• v.14 no.4
• /
• pp.661-670
• /
• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
• /
• v.10 no.1
• /
• pp.27-33
• /
• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.