• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.213-215
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• 2003

Multimedia has to carry data of heterogeous types. Multicast communication techniques can supply the most appropriate infrastructures to such multimedia. Of many multicast protocols, the core based tree (CBT) protocol is the most concentrative studies are conducted on. The CBT places a core router at center of the shared tree and transfers data through the tore router. However, the CBT has two problems due to centralizing all network traffics into a core router. First it can raise bottleneck effect at a core router. Second, it is possible to make an additive processing overhead when core router is distant from receivers. To cope with the problems, this paper proposes an intelligent anycast routing protocol. The anycast routing attempts to distribute the centralized traffic into plural core routers by using a knowledge-based algorithm. The anycast routing estimates the traffic characteristics of multimedia data far each multicast source, and achieves effectively the distributing that places an appropriate core router to process the incoming traffic based on the traffic information in the event that request of receivers are raised. This method prevent the additional overhead to distribute traffic because an individual core router uses the information estimated to multicast sources connected to oneself and the traffic processing statistics shared with other core neuters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1083-1088
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• 2001

In this paper, we propose a new CBT(core-based tree)multicast routing Mechanism by load balancing mechanism. CBT may result in traffic concentration and bottlenecks near the core routers since traffic from all sources nodes the same set of links as approaches the core. So the router have to load packet to new core router for such congestion. Congestion information is given by rtt(round trip time) between designed core router and the other router.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.154-157
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• 2001

In this paper, we propose a new CBT(core-based tree)multicast routing Mechanism by load balancing mechanism. CBT may result in traffice concentration and bottlenecks near the lore routers since traffice from all sources nodes the same set of links as approaches the core. So the router have to load packet to new core router for such congestion. Congestion information is given by rtt(round trip time) between designed core router and the other router.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Journal of KIISE:Information Networking
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• v.30 no.3
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• pp.424-436
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• 2003

In this paper, we propose the Centroid-based Backbone Core Tree(CBCT) generation algorithm for the shared tree-based IP multicasting. The proposed algorithm is based on the Core Based Tree(CBT) protocol. Despite the advantages over the source-based trees in terms of scalability, the CBT protocol still has the following limitations; first, the optimal core router selection is very difficult, and second, the multicast traffic is concentrated near a core router. The Backbone Core Tree(BCT) protocol, as an extension of the CBT protocol has been proposed to overcome these limitations of the CBT Instead of selecting a specific core router for each multicast group, the BCT protocol forms a backbone network of candidate core routers which cooperate with one another to make multicast trees. However, the BCT protocol has not mentioned the way of selecting candidate core routers and how to connect them. The proposed CBCT generation algorithm employs the concepts of the minimum spanning tree and the centroid. For the performance evaluation of the proposed algorithm, we showed the performance comparison results for both of the CBT and CBCT protocols.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.2B
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• pp.130-137
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• 2012

In this paper, we propose core and edge router architectures with LPI(Low Power Idle) for reducing energy consumption in OBS networks. The proposed core router architecture is comprised of a BCP switch, a burst switch, line cards and sleep/wake controller for LPI. When the offered load of network is low, sleep/wake controller can change the state of the core router line card from active to sleep state for saving the energy after receiving network control packet. The edge router consists of a switch for access line card, a SCU and OBS edge router line cards. The LPI function in edge router line card is performed through network level control by network control packet, individually. Additionally, PHY/transceiver modules can transition active state to sleep state when burst assemble engine generates new bursts. To evaluate the energy saving performance of proposed architecture with LPI, the power consumption of each router is analyzed by using data sheet of commercial router and optical device. And, simulation is also performed in terms of sleep time of PHY/Transceiver through OPNET.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1931_1933
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• 2009

NoC 기반 시스템이 적용되는 설계는 시스템 크기가 커짐에 따라 칩 테스트 문제도 동시에 제기 되고 있다. 이에 따라 NoC 기반의 시스템의 테스트 시간을 줄일 수 있는 internal test 방식의 새로운 BIST(Built-in Self-Test) 구조에 관한 연구를 하였다. 기존의 NoC 기반 시스템의 BIST 테스트 구조는 각각의 router와 core에 BIST logic과 random pattern generator로 LFSR(Linear Feedback Shift Register)을 사용하여 연결하는 individual 방식과 하나의 BIST logic과 LFSR을 사용하여 각각의 router와 core에 병렬로 연결하는 distributed 방식을 사용한다. 이때, LFSR에서 생성된 테스트 벡터가 router에 사용되는 FIFO 메모리를 통과하면서 생기는 테스트 타임 증가를 줄이기 위하여 shift register 형태의 FIFO 메모리를 변경하였다 제안된 방법에서 테스트 커버리지 98%이상을 달성하였고, area overhead면에서 효과를 볼 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.34-42
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• 2012

This paper analyses the energy saving basic power models in core IP networks, and proposes the adaptive buffer and burst scheme which is a possible energy saving method, and its implementation algorithm in core IP networks. Especially this paper describes the adaptive buffer and burst scheme dynamically varying the buffering interval B according to the input traffic volume of ingress router, and explains the operation principle of proposed scheme. This method is to adjust the buffering interval B according to input traffic volume of ingress router, that is increasing the interval B when input traffic volume is low, and decreasing the interval B when input traffic volume is high between some given interval regions. This method can gets the high energy saving effect as decreasing the transition number of idle/active in networks when input traffic volume is low, and decreasing the transition number of idle/active by the continuous of burst packets in transit router when input traffic volume is high. This paper shows the increasing of asleep rate for the energy saving of core IP networks and confirms the energy saving of core IP networks by the computer simulation. We confirmed that proposed method can be save the energy of IP networks by properly trade off network performances.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.41-49
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• 2004

Increase of internet users and new types of applied traffics, have led to demand for more bandwidth for each application. Hence, the amount of internet traffic has risen sharply and it has demanded to use limited resources, such as wavelength and bandwidth, more effectively. These kind of needs can be satisfied with OXC(Optical cross-connects) based on GMPLS that carry out IP packet switching and wavelength switching at the same time and Provide very wide bandwidth. In RSVP-TE signaling of GMPLS studied by IETF. every lambda router in core network should be able to convert wavelength. So, lots of wavelength converters and needed and building and managing cost is high. Another problem is that optimized traffic is limited. In this paper We suggest strengthened GMPLS RSVP-TE signaling algorithm for a better lightpath setup. When setup signaling is blocked suggested algorithm does not send PathErr message to Edge Router, but looks for nearest lambda router which can convert wavelength and carry out setup signaling from that node. Such algorithm can reduce the chance of blocked lightpath setup signaling and provide effective arrangement of lambda router in core network by calculating proper number of wavelength converter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.