• Journal of Power System Engineering
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• v.4 no.4
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• pp.59-64
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• 2000

Especially, demands for the noise reduction of mold transformer has been becoming an common issue because it has been used mainly at the residence area such as building and ship. So, this paper investigates the noise source and countermeasure of mold transformer radiated high noise abnormally. The result of impact hammering test for core of transformer ascertains the core resonance by harmonics of line frequency and high noise can be reduced to avoid core resonance by changing torque strength of tie rod. Magnetic field analysis is performed to identify the reason that noise of V-phase is higher than U and W-phase in the normal condition. It is the cause that flux density and magnetic force of V-phase is higher than the other phase respectively.

• Journal of Software Engineering Society
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• v.29 no.2
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• pp.1-6
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• 2020

Software product line development is a development paradigm that efficiently develops a product family by avoiding redundant development based on separation of the common part and the variable part of the product family. In software product line development, the source code that is used to produce a product family is called a product line code base, and when the product line code base is changed and the products of the product family are affected by the change, the activity of testing the affected products is called a product line regression testing. For product line regression testing, instead of conducting regression testing individually on each product of the product family, a more efficient regression testing would be possible if unnecessary testing that are irrelevant to the change can be avoided. This paper introduces SRTS, which is an automated method to efficiently perform software product line regression testing. SRTS divides the product line code base and test cases based on commonality and variability. Then SRTS identifies and selects the test cases affected by the change. Finally, it reduces unnecessary testing by rerunning only the selected test cases.

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.164-170
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• 2014

A single near-field sounde source bearing and ranging method based on a independent doublet array is proposed. In the common case of bearing estimation method, unform linear array or uniform circular array are used. It is constrained retaining aperture because of array structure to estimate the distance of the sound source. Recent using independent doublet array sound source's bearing and distance esmtimation method is proposed by wide aperture. It is limited to the case doublets are located on a straight line. In this paper, we generalize the case and estimate the localization of a sound source in the various array structure. The proposed algorithm was verified performance through simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1244-1255
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• 2017

The space vector pulse width modulation (SVPWM) technique is a popular PWM method for medium voltage drive applications. Conventional SVPWM (CSVPWM) and bus clamped SVPWM (BCSVPWM) are the most common SVPWM techniques. This paper evaluates the performance of various advanced BCSVPWM strategies in terms of their harmonic distortion and switching loss based on a uniform frame work. A uniform frame work, pulse number captures the performance parameter variations of different SVPWM strategies for various number of samples with heterogeneous pulse numbers. This work compares different advanced BCSVPWM techniques based on the modulation index and location of the clamping position (zero vector changing angle ) of a phase in a line cycle. The frame work provides a fixed fundamental frequency of 50Hz. The different BCSVPWM switching strategies are implemented and compared experimentally on a 415V, 2.2kW, 50Hz, 3-phase induction motor drive which is fed from an IGBT based 2 KVA voltage source inverter (VSI) with a DC bus voltage of 400 V. A low cost PIC microcontroller (PIC18F452) is used as the controller platform.

• Journal of the Korean Geotechnical Society
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• v.19 no.2
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• pp.135-146
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• 2003

Uphole test is a seismic field test using receivers on ground surface and a source in depth. In this paper, the uphole test using SPT(standard penetration test) which is economical and reliable for obtaining shear wave velocity profile was introduced. In the proposed uphole test, SPT sampler which is common in site investigation, was used as a source and several 1Hz geophones in line were used as receivers. Test procedures in field and interpretation methods for obtaining interval times and for determining shear wave velocity profile considering refracted ray path were introduced. Finally, uphole test was performed at three sites, and the applicability of the proposed uphole test was verified by comparing wave velocity profiles determined by the uphole test with the profiles determined by downhole test, SASW test and SPT-N values.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.343-346
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• 2004

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.915-921
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• 2013

This work presents a 77 GHz low noise amplifier(LNA) for automotive radar systems using 65 nm RF CMOS process. The LNA is composed of three stage common source amplifiers and includes transmission line matching networks. To reduce the time for three dimensional EM simulation, we optimize the transmission line impedance matching network using a pre-built EM library. The proposed compact simulation technique is confirmed by measurement results. The peak gain of the LNA is 10 dB at 77 GHz and input/output return losses are below -10 dB around the design frequency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.10
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• pp.76-83
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• 2008

The neutral current is made of both the load unbalanced current and the 3rd harmonic. The 3rd harmonic which is the source of the main neutral current is generated from the loads using bridge rectifier circuits on their input produce currents. TV, computer and monitor which are belong to IEC 61000-3-2 Class D are the main 3rd harmonic current sources. In order to show the affect of the distribution system by these disturbances, this paper has studied the current standards of the Korea Electric and considers the problem of the neutral common.