• Journal of IKEEE
• /
• v.27 no.3
• /
• pp.333-339
• /
• 2023

The global market for wearable devices is growing, driving demand for efficient PMICs. Wearable PMICs must be highly energy-efficient despite limited hardware resources. Advancements in process technology enable low-power consumption, but traditional analog LDO regulators face challenges with reduced power supply voltage. In this paper, a novel ADC design with a 3-bit continuous-time flash ADC for the coarse loop and a 5-bit discrete-time SAR ADC for the fine loop is proposed for digital LDO, achieving a 34.78 dB SNR and 5.39 bits ENOB in a 55-nm CMOS technology.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.255-258
• /
• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.25-35
• /
• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.64-69
• /
• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.246-251
• /
• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Journal of IKEEE
• /
• v.11 no.1 s.20
• /
• pp.38-45
• /
• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.8
• /
• pp.1255-1259
• /
• 1990

A new ripple analog-to-digital converter (ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the analog input signal in two serial steps. First, a coarse conversion is made to determine the most significant bits by the first parallel ADC. The resultant bits control the switching network to connect a series resistor segment, within which the analog signal is contained, to the second parallel ADC. At second step, a fine conversion is made to determine the least significant bits by the second parallel ADC. The circuit requires 2(2\ulcorner\ulcorner1) comparators, 2(2\ulcorner\ulcorner resistors, and 2(2\ulcorner\ulcorner swithches for N-bit resolution.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.571-573
• /
• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.1
• /
• pp.76-81
• /
• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Korean Journal of Soil Science and Fertilizer
• /
• v.22 no.4
• /
• pp.280-284
• /
• 1989

The soil texture and the physico-chemical characteristics of 442,000ha reclaimable tide land in the south-western of korean peninsular were analysed. The subsidence which may occur as the soil ripened was studied. The results were as follows : 1. Among the 257,000ha of existing reclaimed tidal land 53.0% was tine silty soil and 36.0% coarse silty, 6.0% coarse loamy and 5.0% sandy soils, respectively. 2. Out of the total 442,000ha of reclaimable tidal land, 51.0% was coarse silty soil, and 20% sandy, 15.0% coarse loamy and 14.0% fine silty textural family, respectively. The coarse silty deposits were mainly distributed in the Gyeong gi and Jeonnam coast, while the coarse deposits(Coarse Loamy-sandy) exist in the Jeonbuk coastal area, but in the Chungnam areas there were various textural grades. 3. Reclaimable tidal Land in the south-western part of the peninsular was Classified into saline and alkaline soil. Electric Conductivity in saturation extract was extremely high that was 46~51 mmhos/cm, E.S.P was more than 25% and pH was ranged around 7.5~8.0 4. Reclaimed to cultivated field the subsidence reclaimable tide land to be expected when was about 18% in Soil and 21% in Sicl soils calculated down to 1.25m of the profile.