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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of ADC for Dual-loop Digital LDO Regulator

이중 루프 Digital LDO Regulator 용 ADC 설계

  • Sang-Soon Park (School of Electrical and Computer Engineering, University of Seoul) ;
  • Jeong-Hee Jeon (School of Electrical and Computer Engineering, University of Seoul) ;
  • Jae-Hyeong Lee (School of Electrical and Computer Engineering, University of Seoul) ;
  • Joong-Ho Choi (School of Electrical and Computer Engineering, University of Seoul)
  • Received : 2023.09.12
  • Accepted : 2023.09.27
  • Published : 2023.09.30
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Abstract

The global market for wearable devices is growing, driving demand for efficient PMICs. Wearable PMICs must be highly energy-efficient despite limited hardware resources. Advancements in process technology enable low-power consumption, but traditional analog LDO regulators face challenges with reduced power supply voltage. In this paper, a novel ADC design with a 3-bit continuous-time flash ADC for the coarse loop and a 5-bit discrete-time SAR ADC for the fine loop is proposed for digital LDO, achieving a 34.78 dB SNR and 5.39 bits ENOB in a 55-nm CMOS technology.

세계적으로 웨어러블 디바이스의 시장이 확장하고 있으며, 이를 위한 효율적인 PMIC의 수요 또한 늘어나고 있다. 웨어러블 디바이스용 PMIC 특성상 높은 에너지 효율과 작은 면적이 필요하다. 프로세스 기술의 발전으로 저전력 설계가 가능하지만, 기존의 아날로그 LDO 레귤레이터는 전원 전압이 낮아짐에 따라 설계의 어려움이 있다. 본 논문에서는 이중 루프 디지털 LDO용 coarse-fine ADC를 제안한다, ADC의 설계는 55 nm CMOS 공정으로 진행하였고 34.78 dB와 5.39 bits의 SNR과 ENOB를 갖는다.

Keywords

Acknowledgement

This work was supported by the Technology Innovation Program (or Industrial Strategic Technology Development Program-Development of DLDO with 99% maximum current efficiency of event-driven asynchronous type without external capacitor)(20016115) funded By the Ministry of Trade, Industry&Energy(MOTIE, Korea)

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