• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.334-340
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• 2006

A compact biosignal monitoring device was developed. Electrodes for electrocardiogram (ECG) and a LED and silicon detector for photoplethysmogram (PPG) were used. A lead II type was arranged for ECG measurement and reflected light was measured at the finger tip for PPG. A single chip microprocessor (model ADuC812, Analog Device) controlled a measurement protocol and processed measured signals. PPG and ECG had a sampling rate of 300 Hz with 8-bit resolution. The maximum power consumption was 100 mW. The microprocessor computed pulse transit time (PTT) between the R-wave of ECG and the peak of PPG. To increase the resolution of PTT, analog peak detectors obtained the peaks of ECG and PPG whose interval was calculated using an internal clock cycle of 921.6 kHz. The device was designed to be operated by 3-volt battery. Biosignals can be measured for $2{\sim}3$ days continuously without the external interruptions and data is stored to an on-board memory. Our system was successfully tested with human subjects.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.680-687
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• 2018

Borehole radar is a radar used for underground resources and geological exploration purposes. It needs a high-speed sampler to transmit electromagnetic waves with a pulse width of several ns and to receive reflected waves of several tens to several hundreds of MHz reflected from the object to be surveyed. ETS (Equivalent-Time Sampling), which can achieve sampling performance of several GHz with a sampling frequency of several tens of MHz, is suitable for use as a sampler of a borehole radar receiver. In this paper, we propose a method to control the sampling clock delay, which is the most important factor in ETS sampler design, using four clocks with phase difference of $90^{\circ}$ for one clock source. The proposed method can reduce the time required to acquire the data within the set interval by 1/25 than the conventional method using the delay generator. When the implemented sampler is applied to the receiver of existing borehole radar, it is possible to accumulate 58 additional times due to the shortened sampling time. In addition, by using one delay control logic compared with the conventional method using several sampling clock delay control logic in order to satisfy the target sampling range, it is possible to omit the correction process which was necessary in the past. As a result, the structure of the system can be simplified and a uniform sampler can be realized.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.1
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• pp.8-13
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• 2003

In this paper, suitablility of 1 GHz CISPR limits establishment fur broadcast communication quality protection is examined and the optimum turn step resolution of EUT for spurious measurement of frequency above 1 GHz to increase the accuracy of maximum values extraction is examined. As a result of 500 MHz and 1.7 GHz clock speed personal computer of micro-processor measurement, optimum turn step resolution extracted by National Institution of National Instrument of Standard & Technology(NIST) Koepke method is estimated 40 table positions per polarization in 500 MHz. And in case of 1.7 GHz, step size is 36 table positions. Prediction of turn step size required for fully scan method in gjgahertz measurement will increase measurement accuracy and reduce considerable measurement time as well.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1026-1030
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• 2015

In this paper, we propose a signal processing board of an optical delay simulator for evaluating a long-range laser range finder and a laser target designator. We improved the accuracy by applying the clock multiplication and the correction of error gradient. To evaluate the performance of the proposed method, we implemented a prototype board and performed experiments. As a result, we implemented the optical delay simulator with resolution less than 0.7m in measuring distance 60km and a standard deviation of 0.041m. The PRF code detection logic and generation logic have a stability less than 0.03% and 0.08% compared to the NATO standard, respectively.