Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design Procedure of Digitally Controlled Oscillator for Power Optimization

디지털 제어 발진기의 전력소모 최적화 설계기법

  • 이두찬 (고려대학교 나노반도체공학과) ;
  • 김규영 (고려대학교 전기전자전파 공학부) ;
  • 김수원 (고려대학교 전기전자전파 공학부)
  • Received : 2009.11.20
  • Published : 2010.05.25
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Abstract

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

본 논문에서는 디지털 제어 발진기의 전력소모를 최적화하는 설계기법을 제안한다. 디지털 제어 발진기의 Coarse tuning 비트수와 Fine tuning 비트수를 조절하여 LSB Resolution, 주파수 범위, 선형성, 이식성에는 영향을 주지 않고 전력소모를 최적화한다. 이를 위해 제어 비트에 따른 디지털 제어 발진기의 전력소모 변화를 분석하였다. 본 논문에서는 0.13um 1.2V CMOS 라이브러리를 이용하여 제안한 설계기법을 적용한 경우와 그렇지 않은 경우를 모두 설계, 모의실험 및 검증하였다. 제안한 설계기법을 적용한 디지털 제어 발진기는 모의실험결과 283MHz부터 1.1GHz의 클록을 생성할 수 있으며, LSB Resolution은 1.7ps이다. 디지털 제어 발진기의 출력 주파수가 1GHz일 때 전력소모는 2.789mW이다.

Keywords

References

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