• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Journal of Astronomy and Space Sciences
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• v.34 no.1
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• pp.19-30
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• 2017

The optical wide-field patrol network (OWL-Net) is a Korean optical surveillance system that tracks and monitors domestic satellites. In this study, a batch least squares algorithm was developed for optical measurements and verified by Monte Carlo simulation and covariance analysis. Potential error sources of OWL-Net, such as noise, bias, and clock errors, were analyzed. There is a linear relation between the estimation accuracy and the noise level, and the accuracy significantly depends on the declination bias. In addition, the time-tagging error significantly degrades the observation accuracy, while the time-synchronization offset corresponds to the orbital motion. The Cartesian state vector and measurement bias were determined using the OWL-Net tracking data of the KOMPSAT-1 and Cryosat-2 satellites. The comparison with known orbital information based on two-line elements (TLE) and the consolidated prediction format (CPF) shows that the orbit determination accuracy is similar to that of TLE. Furthermore, the precision and accuracy of OWL-Net observation data were determined to be tens of arcsec and sub-degree level, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.9
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• pp.941-946
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• 2011

The Loran-C, a radio navigation system based on TDOA measurements is enhanced to eLoran using TOA measurements instead of TDOA measurements. Many error factors such as PF, SF, ASF, clock errors and unknown biases are included in eLoran TOA measurements. Because these error factors can cause failure in eLoran navigation algorithm, these errors must be compensated for high accuracy eLoran navigation results. Compensation of ASF and unknown biases are difficult to calculate, while the others such as PF and SF are relatively easy to eliminate. In order to compensate all errors in eLoran TOA measurements, a simple GPS aided bias compensation method is suggested in this paper. This method calculates the bias as the difference of TOA measurement and the range between eLoran transmitters and the receiver whose position is determined using GPS. The real data measured in Europe are used for verification of suggested method and navigation algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.2
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• pp.125-132
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• 2015

This paper is about analysis of UDRE monitoring method for Korean Satellite navigation system, which is the correction parameter of satellite measurements. New receiver clock bias and tropospheric delay error estimation method to make pseudo-range residual for UDRE monitoring is proposed. Saastamoinen model and Neill mapping function are used for estimate the tropospheric delay and EKF is used for estimgate the receiver clock bias. Through the satellite measurements and regional weather data received directly from the domestic is using for UDRE monitoring analysis, more suitable UDRE monitoring threshold can be deducted and it is expected to be utilized for fault detection technique of Korean Satellite Navigation System.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.4
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• pp.155-161
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• 2014

The purpose of this study is to develop precise point positioning (PPP) algorithms based on GLONASS code-pseudorange, verify their performance and present their utility. As the basic correction models of PPP, we applied Inter Frequency Bias (IFB), relativistic effect, satellite antenna phase center offset, and satellite orbit and satellite clock errors, ionospheric errors, and tropospheric errors that must be provided on a real-time basis. The satellite orbit and satellite clock errors provided by Information-Analytical Centre (IAC) are interpolated at each observation epoch by applying the Lagrange polynomial method and linear interpolation method. We applied Global Ionosphere Maps (GIM) provided by International GNSS Service (IGS) for ionospheric errors, and increased the positioning accuracy by applying the true value calculated with GIPSY for tropospheric errors. As a result of testing the developed GLONASS PPP algorithms for four days, the horizontal error was approximately 1.4 ~ 1.5 m and the vertical error was approximately 2.5 ~ 2.8 m, showing that the accuracy is similar to that of GPS PPP.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.970-973
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• 1996

In this paper, Modified GPS Kalman filter algorithms which allow user to estimate its position when the number of visible GPS satellites becomes less than four are presented. They are derived using the previous estimation of altitude and clock bias. Thus, it is possible to estimate 3-dimensional user position even when only two GPS satellites are visible. The algorithms are ideally suited to car navigation in urban areas where lack of GPS visibility is the major problem because of the frequent blockage of the GPS signals by tall buildings and other structures. Simulation results in this paper show that modified GPS Kalman filter provide better performances than a general GPS Kalman filter or any other instantaneous GPS solution algorithm, especially in the case which the number of visible GPS satellites becomes less than four.