• 산업경영시스템학회지
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• 제23권60호
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• pp.73-81
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• 2000

The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.269-272
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• 1988

This paper deals with the test strategy on the short-open for the printed circuit board. A group testing algorithm, which is the several testing point to be measured redefined as one of the testing points, was suggested. As a result, the total testing time was reduced to 30${\sim}$50 percent.

• 대한전자공학회논문지SD
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• 제38권7호
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• pp.493-502
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• 2001

기존의 논리 테스팅에 비하여 여러 가지 장점을 가지는 전류 테스팅을 위하여 새로운 내장형 전류 감지 회로를 설계하였다. 본 논문에서 제안된 내장형 전류 감지 회로는 시험 대상 회로에서 발생하는 전류와 인버터의 전류 발생 특성에 의해 복사되어진 전류를 비교함으로서 시험 대상 회로의 고장 존재 여부를 감지하여 Pass/Fail 신호로 발생시킨다. 설계된 회로는 차동 증폭 형태의 증폭기와 비교기로 이루어져 있으며, 시험 대상 회로의 전류를 복사해 내기 위한 인버터를 포함하고 있어서 총 10개의 트랜지스터와 3개의 인버터를 사용한다. 본 논문에서 제안된 내장형 전류 감지 회로는 고장 테스트를 위하여 별도의 클럭을 사용하지 않는다. 또한 모드 선택이 필요하지 않아 on-line 테스팅이 가능하며, Pass/Fail 신호를 칩의 외부로 전달하는 출력단자 하나를 제외하고는 별도의 제어단자가 필요하지 않은 장점을 가진다. HSPICE를 사용한 컴퓨터 모의 실험을 통하여 시험 대상 회로에 삽입된 고장을 정확하게 검출해 낼 수 있음을 확인하였다. 제안된 내장형 전류 감지 회로가 칩의 전체 면적에서 차지하는 면적소모는 8×8 병렬 승산기를 시험 대상 회로로 사용한 경우에 약 4.34 %로 매우 작아서 내장형 전류 감지회로에 의한 면적 소모에 대한 부담은 거의 없는 것으로 측정되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.749-752
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• 1999

A new interface circuit for variable resistive sensors is proposed. The interface circuit compose of only two strain gages, a voltage-to-current converter, and current mirror with two outputs. A new dual slope A/D converter based on linear operational transconductance amplifier for the testing of prototype interface circuit is also described. The theory of operation is presented and experimental results are used to verify the theoretical predictions. The results show close agreement between predicted behaviour and experimental performance.

• 한국컴퓨터정보학회논문지
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• 제3권2호
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• pp.99-104
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• 1998

본 논문에서는 다단 논리회로의 고장을 완벽하게 검출할 수 있는 테스트 패턴 생성기를 설계하였다. 이 테스트 기법은 테스트 패턴 생성 논리회로를 사용하여 생성하였다. 생성된 테스트 패턴은 기존의 전체 테스트 방법에 비해 패턴을 크게 감소시켰다. 이 테스트패턴 생성기는 다단 논리회로에서의 모든 고장을 검출할 것으로 본다. 여러 가지 I.C 테스트 방법 중에서 어떤 방법을 선택할 것인지는 고장검출 속도에 영향을 준다. 가장 중요한 것은생산단가이며 설계된 테스트 패턴 생성기는 저가형이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1980-1983
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• 2002

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method fur estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.

• 대한산업공학회지
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• 제40권1호
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• pp.135-139
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• 2014

In a connection-oriented packet switching network, the data communication starts after a virtual circuit is established between source and destination. The virtual circuit establishment time includes the queue waiting times in the direction from source to destination and the other way around. We use this two-way queueing delay to evaluate scheduling policies of a packet switching processor through simulation studies. In this letter, we also suggest user testing functions for the packet switching processor to manage virtual circuits. By detecting error causes, the user testing helps the packet switching processor provide reliable connection-oriented services.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.183-185
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• 2002

This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.

• 한국군사과학기술학회지
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• 제5권1호
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• pp.45-58
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• 2002

In this paper, we designed the circuit of drive control for towing winch. It is composed of reference voltage circuit for driving voltage reference, low pass filter circuit for noise reduction, dead zone circuit for initial transient input, and driving circuit for drum direction/velocity control. Also it is realized a drive control circuit for towing winch drum in accordance with PWM(pulse width modulation) method to suit it's purpose of a large capacity driving system. The performance of the designed circuit is analyzed by experiments and the appliablity for driving the towing winch drum satisfactorily is evaluated through a various testing.

• 대한전기학회논문지:전력기술부문A
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• 제50권6호
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• pp.287-292
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• 2001

This paper deals with the configuration, operating principles, systematic calculation method of parameter and optimization method of test circuit for parallel current injection method, series voltage injection method and hybrid synthetic test method as the method for performance test of circuit breaker with extra high interrupting capacity. The test method depicted above is applied to short-circuit making and breaking test (operating sequence :Os CdOs, Od-CdOs) and out-of-phase tests(operating sequence :Os, CdOs) for performance test of the newly-developed 420kV, 50kA and 800kV 50kV puffer-type gas circuit-breaker according to IEC 60056 and IEC 60427. The testing results, evaluation of equivalence for test and analyzed results are also presented in this paper.