• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.38-40
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• 2002

A study on the test method and the test facilities of synthetic capacitive current tests have been very slight and the direct test method with the short-circuit generator and power transformer only used up to now. However, according to the development of analysis technique of power system and design and manufacture technique we are realized that direct testing method is not satisfactory to evaluate the performance of circuit-breaker because it is difficult to simulate precisely the conditions of power system. Therefore, in order to solve these problem this paper deals with the tests methods and the design technique of the tests facilities of the synthetic capacitive current based on the same theory with the synthetic short-circuit tests.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.305-309
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• 1988

Drawing pneumatic circuits by hand and searching for the error when the circuit is not properly constructed are very difficult. In this paper, a graphic simulation program for drawing and evaluating pneumatic circuit systems was developed. The porgram is menu-driven style and pneumatic circuit can be easily drawn by selecting the pneumatic components from the menus. Simulation of the motion of each pneumatic component and testing of whether the circuit is constructed properly are possible with the software. This program was written in Turbo Pascal and also used the Turbo Graphix Toolbox. The system hardware requires IBM PC, XT, AT or compatibles, and Hercules Card.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1354-1356
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• 2000

This paper deals with a 300kV dc charging system to be used ?s a voltage source in a circuit breaker synthetic short-circuit-test facility. Cockcroft-walton circuit is used to step up the rectified voltage from a single phase transformer of which primary winding is hooked up to an ac220 wall plug. Two systems with the same ratings have been designed and manufactured. The two system have been made of different supporting structure with different insulating materials. The paper describes a couple of charging schemes, system configurations and the synthetic test circuit in which the developed system is to be used.

• Journal of the Speleological Society of Korea
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• no.87
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• pp.8-13
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• 2008

The automatic firewall block and fire alarm system was embodied by using gas circuit and wireless communication equipment, using a smoke sensor (ST-QA1A) and RF Module. OR-CAD was also used for testing circuit system and experiment circuit after assembling circuit. As a result in experiment, the gas sensor detected well an imaginary smoke and worked reliably for driving action of firewall block motor and wireless warning alarm. Through the smoke sensitive perception from the fire, the warning alarm and the preventing fire propagation from the specific closed region were verified reliably. The gas sensor and RF module for firewall and fire alarm system were actually available.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1117-1120
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• 1998

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.299-306
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• 1999

The ${\mu}$-processor based-controlled system is widely used in railway signaling system. The railway signaling systems are highly required safety and reliability. It is necessary to have a fault-tolerant and fail safe concept in ${\mu}$-processor based railway signaling system. In this paper, several architectures and circuits of fault-tolerant computer system is reviewed. The basic concept of the fault-tolerant computer system will be adapted total self checking, strong fail safe, fault display circuit, logic testing circuit and system switching concepts.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.