• Journal of the Semiconductor & Display Technology
• /
• v.22 no.3
• /
• pp.67-72
• /
• 2023

In this paper, a dye-sensitized solar cell (DSSC), one of the representative third-generation solar cells with eco-friendly materials and processes compared to other solar cells, was modeled using MATLAB/Simulink. The simulation was conducted by designating values of series resistance, parallel resistance, light absorption coefficient, and thin film electrode thickness, which are directly related to the efficiency of dye-sensitized solar cells, as arbitrary experimental values. In order to analyze the performance of dye-sensitized solar cells, the optimal value among each parameter experimental value related to efficiency was found using formulas for fill factor (FF) and conversion efficiency.

• ETRI Journal
• /
• v.46 no.2
• /
• pp.238-249
• /
• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• Journal of Advanced Marine Engineering and Technology
• /
• v.39 no.1
• /
• pp.45-51
• /
• 2015

In this paper, we study the RF characteristics of the short wavelength thin-film transmission line employing microstrip line (ML)/coplanar waveguide (CPW) composite structure on silicon substrate for application to RFIC (radio frequency integrated circuit). The thin-film transmission line employing ML/CPW composite structure showed a wavelength shorter than conventional transmission lines. Concretely, at 10 GHz, the wavelength of the transmission line employing ML/CPW composite structure was 6.26 mm, which was 60.5 % of the conventional coplanar waveguide. We also extracted the bandwidth characteristic of the transmission line employing ML/CPW composite structure using equivalent circuit analysis. The S parameter of the equivalent circuit showed a good agreement with measured result. According to the bandwidth extraction result, the cut-off frequency of thin-film transmission line employing ML/CPW composite structure was 377 GHz. Above results indicate that the transmission line employing ML/CPW composite structure can be effectively used for application to broadband and compact RFIC.

• Journal of Biomedical Engineering Research
• /
• v.19 no.3
• /
• pp.251-260
• /
• 1998

The Holter monitoring system is a widely used noninvasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we design a high performance intelligent holter monitoring system which is characterized by the small-sized and the low-power consumption. The system hardware consists of one-chip microcontroller(68HC11E9), ECG preprocessing circuit, and flash memory card. ECG preprocessing circuit is made of ECG preamplifier with gain of 250, 500 and 1000, the bandpass filter with bandwidth of 0.05-100Hz, the auto-balancing circuit and the saturation-calibrating circuit to eliminate baseline wandering, ECG signal sampled at 240 samples/sec is converted to the digital signal. We use a linear recursive filter and preprocessing algorithm to detect the ECG parameters which are QRS complex, and Q-R-T points, ST-level, HR, QT interval. The long-term acquired ECG signals and diagnostic parameters are compressed by the MFan(Modified Fan) and the delta modulation method. To easily interface with the PC based analyzer program which is operated in DOS and Windows, the compressed data, that are compatible to FFS(flash file system) format, are stored at the flash memory card with SBF(symmetric block format).

• Journal of Korea Foundry Society
• /
• v.41 no.6
• /
• pp.550-557
• /
• 2021

With the advent of the fourth industrial revolution, the interest in the internet of things (IoT) in manufacturing is growing, even at foundries. There are several types of process data that can be automatically collected at a foundry, but considerable amounts of process data are still managed based on handwriting for reasons such as the limited functions of outdated production facilities and process design based on operator know-how. In particular, despite recognizing the importance of converting process data into big data, many companies have difficulty adopting these steps willingly due to the burden of system construction costs. In this study, the field applicability of IoT-based devices was examined by manufacturing devices and applying them directly to the site of a centrifugal foundry. For the centrifugal casting process, the temperature and humidity of the working site, the molten metal temperature, and mold rotation speed were selected as process parameters to be collected. The sensors were selected in consideration of the detailed product specifications and cost required for each process parameter, and the circuit was configured using a NodeMCU board capable of wireless communication for IoT-based devices. After designing the circuit, PCB boards were prepared for each parameter, and each device was installed on site considering the working environment. After the on-site installation process, it was confirmed that the level of satisfaction with the safety of the workers and the efficiency of process management increased. Also, it is expected that it will be possible to link process data and quality data in the future, if process parameters are continuously collected. The IoT-based device designed in this study has adequate reliability at a low cast, meaning that the application of this technique can be considered as a cornerstone of data collecting at foundries.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.7
• /
• pp.3425-3430
• /
• 2013

The fast-growing market in wireless communications has led to the development of multi-standard mobile terminals. In this paper, a frequency-tunable active RC bandpass filter for multi-standards wireless communication system is designed using an active inductor. The conventional bandpass filter design methods employ the high order filter or high quality factor Q to improve the stopband attenuation characteristics and frequency selectivity of the passband. The proposed bandpass filter based on the high Q active inductor has an improved frequency characteristics. The center frequency and gain of the designed bandpass filter is tuned by employing the tuning circuit. We have performed the simulation using TSMC $0.18{\mu}m$ process parameter to analyze the characteristics of the designed active RC bandpass filter. The bandpass filter with Q=20.5 has 90MHz half power bandwidth at the center frequency of 1.86GHz. Moreover, the center frequency of the proposed bandpass filter can be tuned between 1.86~2.38GHz for the multi-standards wireless communication system using the capacitor of the tuning circuit.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.1066-1070
• /
• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.2
• /
• pp.132-139
• /
• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.52-62
• /
• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.5 s.347
• /
• pp.128-136
• /
• 2006

In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.