• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.131-135
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• 1999

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.193-215
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• 2003

Fracture Mechanism of Flip Chip Electromigration Failure - Mostly caused by Cathode Depletion at the UBM/Solder Interface Guideline to Increase Electromigration Resistance Material Selection: Sn/Ag(/Cu) > Pb/63Sn Cu UBM > Ni UBM (but, Solder Material combination) UBM Design: thick UBM is preferable (but, Stress Issue) Pad open/UBM size: as large as possible (but, pad size & pitch limit)

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.517-518
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• 2008

Highly integrated ISFETs require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip This paper presents novel packaging type of CMOS ISFET pH sensor using standard CMOS FET chip and extended sensing membrane which is separated from CMOS FET. This proposed packaging type will make it easy to fabricate CMOS ISFET pH sensors

• Food Science and Biotechnology
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• v.16 no.6
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• pp.889-893
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• 2007

The demand of quality green banana chips is increasing in the world snacks market, therefore, the preparation of quality chips and their subsequent shelf life in packaging were evaluated in this study. Banana slices were fried in hot oil to the desired moisture content (2-3%) and oil content (40%) in chips at 3 different temperatures, and the impact of different pretreatments were compared by sensory assessment. A linear relationship between time and temperature was used to achieve the optimal processing conditions. Banana slices fried at the lower temperature of $145^{\circ}C$ took longer to reach the desired chip qualities, but gave the best results in terms of color and texture. Blanching was the most effective pre-treatment for retaining the light yellow color in finished chips. For extending the shelf life of chips, moisture proof packaging in double layer high density polyethylene was more effective than single layer low density polyethylene.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.74-78
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• 2002

MEMS공정을 이용하여 폴리실리콘의 piezoresistivity를 이용한 스트레인 센서어레이를 제작하였고, 이 센서 어레이를 flexible substrate에 패키징하는 공정을 개발하였다. 실리콘 웨이퍼에 표면 가공(surface micromachining)된 센서는 폴리이미드 코팅, release-etch 방법을 통해 웨이퍼로부터 분리되어 폴리이미드를 기판으로 하는 flexible sensor array module을 완성할 수 있었다. 공정은 희생층과 절연층을 증착하고 폴리실리콘 0.5 $\mu\textrm{m}$을 증착, 도핑 및 패터닝하여 센서 어레이를 구성하였다. 이 센서어레이를 flexible substrate에 패키징 하기 위해서 폴리이미드를 코팅하여 15 $\mu\textrm{m}$의 막을 구성하였고, 100% $O_2$RIE를 이용한 선택적 식각 방법으로 via hole을 구성하였다. 이후 전기도금을 통해 회로를 구성하여 1단계 패키징(die to chip carrier)과 2단계 패키징(chip to substrate)을 웨이퍼 레벨에서 완성하였다. 희생층을 제거함으로서 웨이퍼로부터 센서어레이 모듈을 분리하였다. 제작되어진 센서 모듈은 임의의 곡면에 실장이 가능하도록 충분한 flexibility를 얻을 수 있었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.315-321
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• 2005

Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.77-95
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• 2000