• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.14-14
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• 2003

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.253-257
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• 2003

The low temperature flip chip technique is applied to the package of the temperature-sensitive devices for LCD systems and image sensors since the high temperature process degrades the polymer materials in their devices. We will introduce the various low temperature flip chip bonding techniques; a conventional flip chip technique using eutectic Bi-Sn (mp: $138^{\circ}C$) or eutectic In-Ag (mp: $141^{\circ}C$) solders, a direct bump-to-bump bonding technique using solder bumps, and a low temperature bonding technique using low temperature solder pads.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.3-4
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• 2004

A flexible Packaging scheme, which embedded chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending test and finite element analysis. Thinned silicon chips ($t<50{\mu}m$) are fabricated by chemical etching process to avoid possible surface damages on them. These technologies can be use for a real-time monitoring of blood pressure. Our research targets are implantable blood pressure sensor and its telemetric measurement. By winding round the coronary arteries, we can measure the blood pressure by capacitance variation of blood vessel.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.33-37
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified fer other bonding methods such as ACF.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.39-44
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• 2015

We investigated the effect of CNT-Ag composite pad on the contact resistance of flip-chip joints, which were formed by flip-chip bonding of Cu/Au chip bumps to Cu substrate metallization using anisotropic conductive adhesive. Lower contact resistances were obtained for the flip-chip joints which contained the CNT-Ag composite pad than the joints without the CNT-Ag composite pad. While the flip-chip joints with the CNT-Ag composite pad exhibited average contact resistances of $164m{\Omega}$, $141m{\Omega}$, and $132m{\Omega}$ at bonding pressures of 25 MPa, 50 MPa, and 100 MPa, the flip-chip joints without the CNT-Ag composite pad had an average contact resistance of $200m{\Omega}$, $150m{\Omega}$, and $140m{\Omega}$ at each bonding pressure.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.81-86
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• 2003

Electromigration of Sn-3.5Ag solder bump was investigated using flip chip specimens which consisted of upper Si chip and lower Si substrate. While the resistance of the flip chip sample did not almost change until the time right before the failure, the resistivity increased abruptly at the moment when complete failure of the solder joint occurred in the flip chip sample. At current densities of $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$, the activation energy for electromigration of the Sn-3.5Ag solder bump was characterized as ∼0.7 eV. Failure of the Sn-3.5Ag solder bump occurred at the solder/UBM interface due to the formation and propagation of voids at cathode side of the solder bump.