• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• 한국전기전자재료학회논문지
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• 제16권6호
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권9호
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• pp.466-470
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• 2001

We have developed a sub-micron gap fabrication technology using chemical-mechanical polishing (CMP) without /the sub-micron lithography equipments (0.18∼0.25 7m). And it has been applied to a lateral field emission device (FED), in which narrow gap distance is very important for reducing turn-on voltage. As a result, the turn-on voltage (at which the current level is 1 nA) of the fabricated device with the gap distance of 256 nm is as low as 4.0 V, which is the lowest turn-on voltage among lateral FEDs ever reported.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권12호
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• pp.549-554
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• 2006

In this paper we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity between electrode and ferroelectric film. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of PZT films. Removal rate, WIWNU% and surface roughness have been found to depend on slurry abrasive types and their hardness, especially, surface roughness and planarity were strongly depends on its pH value. A maximum in the removal rate is observed in the silica slurry, in contrast with the minimum removal rate occurs at ceria slurry. We found that the surface roughness of PZT films can be significantly reduced using the CMP technique.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.113-114
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• 2005

Sufficient removal rate with adequate selectivity to realize the pattern mask of tetra-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained by chemical mechanical polishing (CMP) with commercial silica slurry as a function of pH variation. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.567-568
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• 2006

To investigate the recycle possibility of slurry for the oxide-chemical mechanical polishing (oxide-CMP) application, three kinds of retreated methods were introduced as follows: First, the effects on the addition of silica abrasives and the diluted silica slurry (DSS) on CMP performances were investigated. Second, the characteristics of mixed abrasive slurry (MAS) using non-annealed and annealed alumina ($Al_2O_3$) powder as an abrasive added within DSS were evaluated to achieve the improvement of removal rates (RRs) and within-wafer non-uniformity (WIWNU%). Third, the oxide-CMP wastewater was examined in order to evaluate the possible ways of reusing it. And then, we have discussed the CMP characteristics of silica slurry retreated by mixing of original slurry and used slurry (MOS).

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.441-442
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• 2002

Chemical mechanical polishing (CMP) is a manufacturing process that uses controlled wear to planarize dielectric and metallic layers on silicon wafers. CMP experiments revealed that a sub-ambient film pressure developed at the wafer/pad interface. Additionally, dishing occurs in CMP processes when the copper-in-trench lines are removed at a rate higher than the barrier layer. In order to study dishing across a stationary wafer during polishing, dishing maps were created. Since dishing is a function of the total contact pressure resulting from the applied load and the fluid pressure, the hydrodynamic pressure model was refined and used in an existing model to study copper dishing. Density maps, highlighting varying levels of dishing across the wafer face at different radial positions, were developed. This work will present the results.