• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.78.2-78
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• 2003

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.29.2-29
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• 2003

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.361-362
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• 2008

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.106.1-106
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• 1998

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.485-485
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• 2009

Double side polishing process has been used for various industrial applications, such as polishing of semiconductor substrates and flat panel display glasses. In wafer manufacturing, double side polishing process is applied to improve wafer flatness and to minimize particle generation from wafers in device manufacturing processes, which is recognized as one of the most important processes. Whereas the kinematical modeling and analysis results of single side polishing, extensively used for chemical-mechanical polishing (CMP) in device manufacturing, are well investigated, the studies in conjunction with double side polishing are barely carried out, due to the complication of polishing system and the uncertainty of wafer motion in the carrier. This paper suggests the derivation of kinematical model with consideration of carrier and wafer motion in double side polishing, and then presents the effect of kinematical parameters on material removal amount and its non-uniformity. The kinematical analysis results help to understand the double side polishing process and to control the polishing results.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.107-108
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• 2005

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.103-104
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• 2006

In this paper. we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interlace. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then. we compared the structural characteristics before and alter CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.83-84
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• 2006

Chemical mechanical polishing (CMP) process has been attracted as an essential technology of multi-level interconnection. However, the COO (cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. Also, the addition effects of $MnO_2$ abrasives and the diluted silica slurry (DSS) on CMP performances were evaluated. Finally, we have investigated the possibility of new abrasive for the oxide CMP application.