Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Development of Cu CMP process for Cu-to-Cu wafer stacking

Cu-to-Cu 웨이퍼 적층을 위한 Cu CMP 특성 분석

  • Song, Inhyeop (Microsystems Packaging Center Seoul Technopark) ;
  • Lee, Minjae (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National Univ. of Science and Technology)
  • 송인협 (서울테크노파크 MSP센터) ;
  • 이민재 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김사라은경 (서울과학기술대학교 NID융합기술대학원)
  • Received : 2013.09.13
  • Accepted : 2013.12.03
  • Published : 2013.12.30
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Abstract

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

웨이퍼 적층 기술은 반도체 전 후 공정을 이용한 효과적인 방법으로 향후 3D 적층 시스템의 주도적인 발전방향이라고 할 수 있다. 웨이퍼 레벨 3D 적층 시스템을 제조하기 위해서는 TSV (Through Si Via), 웨이퍼 본딩, 그리고 웨이퍼 thinning의 단위공정 개발 및 웨이퍼 warpage, 열적 기계적 신뢰성, 전력전달, 등 시스템적인 요소에 대한 연구개발이 동시에 진행되어야 한다. 본 연구에서는 웨이퍼 본딩에 가장 중요한 역할을 하는 Cu CMP (chemical mechanical polishing) 공정에 대한 특성 분석을 진행하였다. 8인치 Si 웨이퍼에 다마신 공정으로 Cu 범프 웨이퍼를 제작하였고, Cu CMP 공정과 oxide CMP 공정을 이용하여 본딩 층 평탄화에 미치는 영향을 살펴보았다. CMP 공정 후 Cu dishing은 약 $180{\AA}$이었고, 웨이퍼 표면부터 Cu 범프 표면까지의 최종 높이는 약 $2000{\AA}$이었다.

Keywords

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