• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.1-240.1
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• 2013

본 연구에서는 Symmetric NMOSFET의 channel length에 따른 전기적 특성 분석에 관한 연구를 진행하였다. 특성 분석에 사용된 소자의 Gate oxide 두께는 6 nm 이며, 채널 Width/Length는 각각 10/10 ${\mu}m$, 10/0.2 ${\mu}m$ 이다. Drain Avalanche Hot Carrier(DAHC) 테스트를 진행하기 위하여 각각 스트레스 조건을 추출하였고, 조건에 해당되는 스트레스를 1700초 동안 인가하였다. 스트레스 후, Channel length가 10 ${\mu}m$과 0.2 ${\mu}m$인 두 소자의 특성을 측정, 분석결과 10 ${\mu}m$의 소자의 경우 문턱전압(VT)과 Subthreshold swing (SS)의 변화가 없었지만 0.2 ${\mu}m$의 소자의 경우 0.42V의 (from 0.67V to 1.09V) 문턱전압 변화 (VTH)와 71 mV/dec (from 79 mV/dec to 150 mV/dec))의 Swing (SS)변화를 보여 스트레스 후에 Interface trap이 증가하였음을 알 수 있다. off-state leakage current를 측정 결과 0.2 ${\mu}m$ 의 경우 leakage current의 양이 증가하였음을 알 수 있고 이는 드레인 부근에 증가된 interface trap에 의한 현상으로 판단된다. 상기 결과와 같이 DAHC 스트레스에 의한 소자의 열화 현상은 Channel length가 짧을수록 더 크게 의존하는 것을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.169-172
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• 2020

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.51-54
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• 1996

This paper reports the studies of the inversion layer mobility in p-channel Si MOSFET's under hot-carrier degradated condition. The validity of relationship of hot carrier degradations between the surface effective mobility and field effect mobility and are examined. The effective mobility(${\mu}$$\_$eff/) is derived from the channel conductances, while the field-effect mobility(${\mu}$$\_$FE/) is obtained from the transconductance. The characteristics of mobility curves can be divided into the 3 parts of curves. It was reported that the mobility degradation is due to phonon scattering, coulombic scattering and surface roughness. We are measured the mobility slope in curves with DC-stress [V$\_$g/=-3.1v]. It was found that the mobility(${\mu}$$\_$eff/ and ${\mu}$$\_$FE/) of p-MOSFET's was increased by increasing stress time and decreasing channel length. Because of the increasing stress time and increasing V$\_$g/ is changed oxide reliability and increased vertical field.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.49-56
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• 1993

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.30-37
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• 1993

In this paper, we present a simple and general lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and gate current influence to solve a problem that that I$_{b}$ is dependent on drain structure. The suggested model is applied to a different channel, drain structured PMOSFET. For all PMOSFETs, dg$_{m}$/g$_{m}$ of PMOSFET appears with one straight line about Q$_{g}$, therefore, this model using I$_{g}$ is consistent with experiment result independently of channel, drain structure. It is, therefore, proposed that a model using I$_{g}$ has a general applicability for PMOSFET's.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.15-19
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• 2010

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.93-97
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• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.