• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.793-799
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• 2006

In this paper, the gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. the gate to drain current has been obtained with ground source. The difference between two currents has been tested and proves that the electric field generated by channel charge effect against the image force lowering.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1033-1041
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• 1990

In this paper, under pinch-off conditions, the gate-drain breakdown voltage characteristics of GaAs Power MESFET's as a function of device parameters such as channel thickness, doping concentration, gate length etc. are analyzed. Using the Green's function, the gate ionic charge induced by the depleted channel ionic charge is calculated. The impact ionization integral by avalanche multiplication between gate and drain is used to investigate breakdown phenomena. Especially, the localized excess surface charge effect as well as the uniform surface charge effect on breakdown voltage is considered.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• 생명과학회지
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• 제16권1호
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• pp.37-43
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• 2006

간극결합은 이웃하는 두 세포 사이에 형성된 이온채널이며 또한 단일세포막에서도 작용한다. 간극결합채널을 형성하는 아미노 말단의 10번째 아미노산 잔기 부위까지가 개폐극성(gating polarity)과 전류-전압관계에 영향을 미친다. 정상적인 Cx32 채널은 음성의 개폐극성과 내향적인 정류현상을 보이는 반면, 음성전하를 띠는 aspartate로 치환된 T8D 채널은 반대의 개폐극성과 직선의 정류현상을 보인다. 이러한 개폐극성과 정류현상의 변화가 전하 자체에 의한 것인지 아니면 아미노 말단의 구조적인 변화에 의한 것인지는 아직 불명확하다. 이러한 문제점을 규명하기 위하여 아미노 말단의 8번째 아미노산 잔기를 cysteine기로 치환시킨 T8C 채널을 만들어 substituted-cysteine accessibility method (SCAM) 방법으로 이 채널의 생물리학적 특성을 조사하고자 하였다. T8C 채널은 정상적인 Cx32 채널처럼 음성의 개폐극성과 내향적인 정류현상을 보였으며, cysteine기로 치환이 정상적인 Cx32 채널의 원래 구조를 변화시키지 않았다는 것을 의미한다. 본 연구에서는 이런 전하효과를 규명하기 위하여 음성 전하를 갖는 MTSES-와 양성전하를 갖는 MTSET+를 사용하였다. MTSES-를 처리하면 T8C 채널은 T8D 채널의 특성처럼 양성의 개폐극성과 직선의 정류현상을 보였다. 그러나 양성전하를 갖는 MTSET+를 처리한 경우에는 T8C 채널은 본래의 특성을 그대로 유지하였다. 작은 분자의 MTS에 의해서 부여된 전하가 아미노 말단의 구조적인 변화를 초래하지는 않을 것으로 생각된다. 따라서 반대의 전하를 띠는 MTSES-와 MTSET+가 서로 상반대는 영향을 미치는 것으로 보아 본 연구에서 관찰된 개폐극성과 전류-전압의 변화는 아미노말단의 구조적인 변화라기보다는 MTS에 의해서 부여된 전하 자체에 기인한다고 할 수 있다. 또한 MTS가 아미노말단의 8번째 부위에 접근하여 반응을 일으킬 수 있다는 결과는 간극결합채널의 아미노말단이 채널의 통로(pore)를 형성한다는 가설을 뒷받침한다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.726-728
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• 2012

본 논문에서는 채널의 두께 변화에 따른 Double Gate MOSFET의 문턱전압특성을 분석 하였다. 채널의 두께는 소자의 크기를 결정할 뿐만 아니라 단채널효과에도 커다란 영향을 미치므로 IC 설계시 매우 중요한 파라미터이다. 그러므로 본 연구에서는 급수형 전하분포를 이용하여 채널두께에 따른 DGMOSFET의 문턱전압을 분석하였으며 이를 통해 채널의 두께가 증가할수록 문턱전압은 감소한다는 결과를 얻었다.