• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.37-43
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• 2009

This paper describes a monolithic Darlington-cascade amplifier (DCA) operating at X-band, realized with a 0.35-micron SiGe bipolar process, which provides 45 GHz $f_T$. A conventional cascade amplifier was also designed on the same process and tested to establish a reference. Compared to the reference cascade amplifier, the proposed monolithic amplifier circuit exhibits an improved gain of 2.5 dB and improved output power 1-dB compression point of 5.2 dB with 72% wider bandwidth. Measurement results show 19.5 dB gain, 11.2 dBm 1-dB compression power, and 3.1 GHz bandwidth. These results demonstrate that the Darlington-cascade cell is an advantageous substitute to the conventional cascade amplifier.

• 전기의세계
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• v.29 no.12
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• pp.798-803
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• 1980

A computer program for noise analysis of the audio circuit is developed. The application of the program to the equalizer, low frequency amplifier of radio circuit and cascaded amplifier show good results. The general noise analysis method for cascade operational amplifier is presented. The noise spectral power density is calculated for a resonator active filter.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.1-7
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• 2012

In this paper, An X-band solid state power amplifier(SSPA) for pulse compressed microwave signal with 60Watt power and power added efficiency(PAE) above 30% is described. Designed 60Watt high power amplifier(HPA) was implemented by cascade coupled amplifiers, and it is consisted on three stage drive amplifiers with internally matched GaAs FET and one stage main power amplifier with an internally matched GaN HEMT. The designed SSPA has performance with more than total power gain 37dB and output power 48dBm(60-W) in condition of frequency range $9.41{\pm}0.03GHz$, pulse period width under 1ms and duty cycle under 10%. The implemented SSPA can apply to high quality digital marine radar applications with pulse compression technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.125-131
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• 2002

This paper presents MMIC drive and power amplifiers covering 6-18 ㎓. For simple wideband impedance matching and less sensitivity to fabrication variation, modified distributed topologies are employed in the both amplifiers. Cascade amplifiers with a self-biasing circuit through feedback resistors are used as unit gain blocks in the drive amplifier, resulting in high gain, high stability, and compact chip size. Self impedance matching and high-pass, low-pass impedance matching networks are used in the power amplifier. In measured results, the drive amplifier showed good return losses ($S_11,{\;}S_{22}{\;}<{\;}-10.5{\;}dB$), gain flatness ($S_{21}={\;}16{\;}{\pm}0.6{\;}dB$), and $P_{1dB}{\;}>{\;}22{\;}dBm$ over 6-18 GHz. The power amplifier showed $P_{1dB}{\;}>{\;}28.8{\;}dBm$ and $P_{sat}{\;}{\approx}{\;}30.0{\;}dBm$ with good small signal characteristics ($S_{11}<-10{\;}dB,{\;}S_{22}{\;}<{\;}-6{\;}dB,{\;}and{\;}S_{21}={\;}18.5{\;}{\pm}{\;}1.25{\;}dB$) over 6-18 GHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.42-50
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• 1984

The method of increasing the bandwidth of distributed amplifier by the feedback loop is presented in this paper. In this method, it is tried to increase the gain of the amplifier in the high frequency range by giving a positive feedback on the device, while giving no influence in the low frequency range. For the simplicity of the amplifier design the transmission line theory of periodical structure with a unilateral divice is used in the design, and the 2-ports cascade network theory developed by K.B. Niclas is used in computer analysis for the purpose of precise results. In this simulation, the bandwidth of the amplifier is increased from 16 [GHz] without feedback loop to about 20 [GHz] with the feedback loop.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.193-194
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• 2007

This paper presents the design of a power amplifier for full-band UWB application systems using a CMOS 0..18um technology. A wideband RLC filter and a multilevel RLC matching scheme are utilized to achieve the wideband input/output matching. Both the cascade and cascode stage are used to increase the gain and to achieve gain flatness. Simulation results show that the designed amplifier provides a power gain greater than 10 dB throughout the UWB full-band(3.1-10.6GHz) and an input P1dB of -1.2dBm at 6.9GHz. It consumes 35.8mW from a 1.8V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.33-40
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• 1998

In this paper, a design of current-mode continuous-time filters for low voltage and low frequency applications using complementary bipolar current mirrors is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integration. Since the design method of the proposed current-mode filters are based on the integrator type of realization, it can be used for a wide range of applications. Since the input impedance of simple bipolar current mirror is small, in this paper, negative feedback amplifier is used to realize is designed by cascade method. The cutoff frequency of the designed filter can be easily tunable by the DC controlling current from 60kHz to 120kHz. The characteristics of the designed current-mode filters are simulated and examined by SPICE using standard bipolar transistor parameters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1359-1368
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• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.