• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.937-940
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• 2000

This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• 한국통신학회논문지
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• 제14권3호
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• pp.189-196
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• 1989

본 논문에서는 BICMOS 게이트 어레이 시스템 구성시 내부의 논리회로 부분은 CMOS 소자로 입출력부는 바이폴라 소자를 이용할 수 있는 공정과 소자 개발을 하고자 하였다. BICMOS게이트 어레이 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS 소자 각각의 특성을 좋게 하는데 두었다. 시험결과로서, npn1 트랜지스터의 hFE 특성은 120(Ic=1mA) 정도이고, CMOS 소자에서는 n-채널과 p-채널이 각각 1.25um, 1.35um 까지는 short channel effect 현상이 나타나지 않았고, 41stage ring oscillator의 게이트당 delay 시간은 0.8ns이었다.

• 한국통신학회논문지
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• 제18권3호
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• pp.397-409
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• 1993

본 논문은 전류 모드 COMS 다치논리회로를 이용하여 CLA 방식에 의한 8비트 2진 병렬 가산기의 설계를 제안하였고, $5{\mu}m$의 표준 반도체 기술을 이용하여 시뮬레이션하였다. m치의 다치논리회로에 의한 CLA 방식의 가산기 설계시 필요한 발생캐리 $G_K$와 전달캐리 $P_K$의 검출조건을 유도하였고, 이를 4치에 적용하였다. 또한 4치 논리회로와 2진 논리회로의 결합에 의한 연산시 필요한 엔코더, 디코더, mod-4 가산회로, G_k및 P_k 검출회로, 전류-전압 변환회로를 CMOS로 설계하였다. 또한 시뮬레이션을 통해 각 회로의 동작을 검증하였으며, 다치회로의 장점을 이용한 2진 연산에 응용을 보여주었다. 순수한 2진 및 CCD-MVL에 의한 가산기와의 비교를 통해, 제안한 가산기는 1개의 LAC 발생기를 사용하여 1 level로 구성가능하며, 표준 CMOS 기술에 의한 4차 논리회로가 실현 가능하므로 다치논리회로의 유용성을 보였다.

• 전자공학회논문지B
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• 제29B권9호
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• pp.27-36
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• 1992

A design of scanning electrode driving IC chip has been implemented aiming at the application to liquid crystal color television displays. The chip reflects the design characteristics of high quality liquid crystal panels and satisfies specifications of NTSC type color television displays. The design was verified using logic and circuit simulation, and fabricated using a high voltage CMOS process. A fully working die has been obtained that can be readily applicable to commercial color liquid crystal panels.

• 전자공학회논문지A
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• 제30A권2호
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• 한국전기전자재료학회논문지
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• 제30권9호
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.