• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.239-247
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• 2007

In this paper, we propose a system that the Linux is ported in embedded system with peripheral devices of CIS(CMOS Image Sensor) and GPS module. The system acquires GGA sentence from GPS module by recognizing camera and GPS is used module in Linux kernel. And then the received location information is used to include still image acquired through CIS According to this paper, We compose hardware for embedded system, attach board (including camera), port Linux BootLoader and Kernel. And. then we realize that it insert kernel in CIS control device driver and GPS module device driver.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.132-139
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• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.116-123
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• 2007

This paper proposed a new amplitude width modulation for OLED data driver IC. The data driver controls brightness of OLED by adjusting amplitude and width of the data drive current pulse. There were two conventional methods; pulse amplitude modulation(PAM) and pulse width modulation(PWM). The PWM method suffered from lower light emitting time efficiency at low luminance signal. The PAM method suffered from large chip area using DACs for each column. The proposed method was aiming at accurately controlling of the current level by MSB data and light emitting efficiency by LSB data to improve the inefficiencies of the PAM and a PWM. The proposed AWM driver circuit implemented using $0.35-{\mu}m$ 3-poly 4-metal CMOS high voltage process. The simulation result shows the improvement in the accuracy of the gray level control even though the driver circuit is smaller than the PAM.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.1-8
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• 2012

This paper presents a fully-integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also proposes a low-swing gate driver for efficient regulation of high-frequency switching converters. The low-swing driver uses the voltage drop of a diode-connect transistor. The proposed converter is designed and fabricated using a $0.13-{\mu}m$ CMOS process. The fully-integrated buck converter achieves 68.7% and 86.6% efficiency for 3.3 V/2.0 V and 2.8 V/2.3 V conversions, respectively.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• ETRI Journal
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• v.34 no.6
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.