• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.13-22
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• 1991

In this paper we designed 2 bit ECC(Error Checking and Correction) circuit using Single Layer Perceptron type neural networks. We used (11, 6) block codes having 6 data bits and 8 check bits with appling cyclic hamming codes. All of the circuits are layouted by CMOs 2um double metal design rules. In the result of circuit simulation, 2 bit ECC circuit operates at 67MHz of input frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.118-123
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• 1989

In this paper, as we have integrated SCF for voice signal processing using CMOS circuit with the low power dissipation and the easy circuit design, it has been presented the simplified CMOS OP AMP design method with ${\pm}$5V pwoer source in order to use together with digital part. After an example about SCF CMOS OP AMP design, it has been performed layout appling channel width and length obtained by design method, and then its characteristics were simulated by SPICE 2G program. Therefoe, this design method will be applied the general CMOS OP AMP design in the electronic circuit.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.65-71
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• 2010

This paper presents a 14-band LO generator architecture for MB-OFDM UWB systems using 3.1 GHz~10.6 GHz frequency band. The proposed LO generator architecture has been consisted of only one PLL and the fewest nonlinear components to generate 14 LO signals with high purity while consuming low dc power consumption. In addition, major spurious generated from the LO generator have been located in the out of UWB band. The proposed LO generator has been implemented in a $0.13-{\mu}m$ CMOS technology and consumes a dc power consumption of 93~103 mW from a 1.5 V supply. The simulation results show an in-band spurious suppression ratio of more than 41 dBc and a band-switching time of below 3 nsec.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.