• Journal of Digital Contents Society
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• v.6 no.1
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• pp.41-48
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• 2005

In this paper, we propose and evaluate symbol timing recovery algorithm for S-DMT cable modern, which supports more channels and better quality symmetric mutimedia service over HFC network. We adopt timing recovery algorithm of PN sequence insertion in time domain and evaluate the performance of it in various noise channel such as AWGN, ISI, impulse. We verified that performance of this algorithm is depends on the channel noise environment and sampling clock offset and that over 10 dB degradation of Eb/No is occurred at the timing failure probability of $10^3$ in the composite noise channel of AWGN, ISI, and impulse in comparison with impulse noise-alone channel. finally, we verified that this algorithm showed good timing failure probability in case of sampling clock optimization was performed in advance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1609-1617
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• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.840-847
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• 2001

본 논문에서는 클럭 동기 회로에 사용되는 다차 함수 형태의 결합 필터를 선형 근사화 하는 알고리즘을 제안하고 이를 하드웨어로 구현한다. 정합 필터와 보간필터에 의한 클럭 동기회로는 수신기를 전 디지털 회로를 구현하기 위해 선호되지만 계산량이 증가하는 단점이 있다. 본 논문에서는 정합 필터의 임펄스 응답을 갖는 결합 보간 필터를 구현하고, base 함수의 적용을 선형 근사화 하여 필터의 계산량을 감소시켰다. 본 논문에서는 선형 근사화된 결합 보간 필터의 동작을 Matlab을 통한 시뮬레이션과 ALTERA Chip으로 테스트하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.30-36
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• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.76-85
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.331-339
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• 2018

The IEEE 1588, commonly known as a precision time protocol (PTP), is a standard for precise clock synchronization that maintains networked measurements and control systems. The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for PTP. The BMC allows a slave clock to automatically take over the duties of the master when the slave is disconnected due to a link failure and loses its synchronization; the slave clock depends on a timer to compensate for the failure of the master. However, the BMC algorithm does not provide a fast recovery mechanism in the case of a master failure. In this paper, we propose a technique that combines the IEEE 1588 with network bonding to provide a faster recovery mechanism in the case of a master failure. This technique is implemented by utilizing a pre-existing library PTP daemon (Ptpd) in Linux system, with a specific profile of the IEEE 1588 and it's controlled through bonding modes. Network bonding is a process of combining or joining two or more network interfaces together into a single interface. Network bonding offers performance improvements and redundancy. If one link fails, the other link will work immediately. It can be used in situations where fault tolerance, redundancy, or load balancing networks are needed. The results show combining IEEE 1588 with network bonding enables an incredible shorter recovery time than simply just relying on the IEEE 1588 recovery method alone.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.12
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• pp.981-987
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• 2000

이 논문은 상위 단계 데이터-경로 합성에서 연산 스케쥴링과 자원 할당 및 배정을 동시에 고려한 통합적 접근 방법을 제시한다. 제안한 방법은 스케쥴링 되어있지 않은 데이터-플로우 그래프에 대해서 수행에 필요한 총 clock 스텝 수와 필요한 회로 면적을 동시에 최소화하는 데이터-경로 생성에 특징이 있다. 일반적으로, 연결선의 결정이 합성의 마지막 단계에서 이루어지는 기존의 방법과는 다르게, 우리의 접근 방법은 연산 스케쥴링과 연산의 연산 모듈 배정 그리고 변수의 레지스터 배정 작업을 동시에 수행하여 추가적인 연결선의 수를 매 clock 스텝마다 최적화(optimal) 시킨다. 본 논문은, 이 문제를 최소-비용의 최대-플로우 문제로 변형하여 minimum cost augmentation 방법으로 polynomial time 안에 해결하는 알고리즘을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.