• Title/Summary/Keyword: Bus Design

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DID Bus Station Design for Daejeon City (대전광역시의 버스 정류장 디자인)

  • Yim, Oh-Yon
    • Proceedings of the Korean Institute of Interior Design Conference
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    • 2008.05a
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    • pp.86-89
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    • 2008
  • In this paper, bus station design is presented as a component of public design to develop the integrated city public image of Daejeon Metropolitan City through the study of city characteristics and the direction of future development. Design concept is the mutual understanding of public image and human centered sense, and comfortable bus station which is correspond with future development direction and applicable for digital informationization is selected. Design components are bus shelter, information board, bench, vending machine, a wastebasket, billboards and so forth.

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A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design

  • Yoon, Myungchul
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.436-442
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    • 2014
  • A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

Design and Implementation of a Bus Monitoring Instrument for the TICOM-III Integration Test and Performance Analysis (고속 중형 컴퓨터 통합 시험 및 성능 분석을 위한 버스 감시기의 설계 및 구현)

  • 한종석;송용호
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.8
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    • pp.1064-1073
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    • 1995
  • On a bus-based shared memory multiprocessing system, the system bus monitoring and analysis are crucial for system integration test and performance analysis. In this paper, the design and implementation of a bus monitoring instrument for the TICOM-III system are decribed. The instrument dedicated to TICOM-III, which is called the Bus Information Procssing Unit, analyzes the bus state and measures the bus utilization. It performs many useful functions to help debugging the system, and offers a simple user interface.

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Low-Power Bus Driven Floorplan for Segmented Bus Design (버스 분할 설계를 위한 저전력 버스 기반 평면계획)

  • Yoo, Jae-Min;Rim, Chong-Suk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.134-139
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    • 2006
  • In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

A Design of an Effective Bus-Invert Coding Circuit Using Flip-Driver (Flip-Driver를 이용한 효율적인 Bus-Invert Coding 회로의 설계)

  • Yoon, Myung-Chul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.69-76
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    • 2007
  • A new circuit design for Bus-Invert Coding is presented in this paper. The new scheme sends the coding information through the bus-lines instead of the invert-line which has been used conventionally for many types of Bus-Invert algorithms. By employing a newly developed bus-driver called Flip-Driver and a selection circuit, it not only removes the invert-line but suppresses the additional bus-transitions in sending coding information. It is verified by simulations that the efficiency of various Bus-Invert algorithms is increased about 40% to 100% by employing the new design.

Protocol Design for Bus Network Communication between Onboard Signalling System and MMI (차상신호장치와 MMI간 버스형 네트워크 통신프로토콜 설계)

  • Kim, Seok-Heon;Han, Jae-Mun;Jung, Ji-Chan;Cho, Yong-Gee
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.2782-2786
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    • 2011
  • In this paper a protocol design for bus network communication between onboard signalling system and MMI(Man Machine Interface) will be presented and illustrated. Recently, many onboard signailling systems adopt hot standby for safety reasons. Hot standby is a method of redundancy in which the primary and secondary systems run simultaneously. It is convenient to use bus network(bus topology) in a hot standby system for communication between onboard signalling system and MMI. Because bus network is the simplest way to connect multiple clients such as onboard signalling system, MMI and etc. However, there are many problems when two clients want to transmit at the same time on the same bus. A effective protocol is necessary to solve that problems. We will describes protocol design which is useful when onboard signalling systems and MMIs are connected via RS485(Bus Network).

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A GA-based Floorplanning method for Topological Constraint

  • Yoshikawa, Masaya;Terai, Hidekazu
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1098-1100
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    • 2005
  • The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

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Optimal Design Considerations of a Bus Converter for On-Board Distributed Power Systems

  • Abe, Seiya;Hirokawa, Masahiko;Shoyama, Masahito;Ninomiya, Tamotsu
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.447-455
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    • 2009
  • The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.

Evaluation on Low-floor Bus Package Layout from the Perspective of Universal Design

  • Kim, Sun-Woong;Kim, Ji-Yeon;HwangBo, Hwan;Hwang, Bong-Ha;Moon, Yong-Joo;Ji, Young-Gu
    • Journal of the Ergonomics Society of Korea
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    • v.30 no.5
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    • pp.659-669
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    • 2011
  • Objective: The aim of this study is to suggest a package layout guideline for low-floor bus by interview with passengers and observations of their behavior. Background: Increasing attention has been introduced the low-floor bus to be more suitable for use by transportation handicapped. Complex issues are involved in providing comfortable services to all people. We are going to suggest package layout guidelines for more comfortable and suitable travel to all people. Method: The two times of survey and video observation sessions were conducted on low-floor buses in Seoul; (1) a finding of potential issues in the first session, (2) a confirming of issues from the last session. Results: The three of major issues were founded in this study; (1) difficulties in supporting body when standing, (2) difficulties in sitting on front wheel pan seat, (3) difficulties in passing through the aisle. Conclusion: There were clear differences between public and transportation handicapped in using some tools which are used for support body such as roof hand rails, side hand rails, and hand rail rings. Some of design problems were founded to improve from the perspective of ergonomics and universal design. Such differences and design guidelines have to be considered in bus design as well as commercial vehicle. Application: The proposed design guidelines can be used to development of low-floor bus and other public transportations.