• 한국정보전자통신기술학회논문지
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• 제14권5호
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• pp.430-437
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• 2021

본 논문에서는 DCGAN 기반의 크로스 레이어 보상 방법을 이용하여 소프트에러의 영향을 줄이는 얼굴인식 기법을 제안한다. JPEG 파일의 데이터 블록에서 소프트에러가 발생할 때, 이 블록들은 제대로 복호화되지 않을 수 있다. 이전 연구에서 해당 블록들은 얼굴 사진들의 평균 이미지를 이용해 대체하였으며, 인식률을 어느 정도 향상하였다. 본 논문에서는 이전 연구의 확장으로 DCGAN 기반의 보상 기법을 다룬다. 패리티 비트 검사기를 이용하는 임베디드 시스템 레이어에서 소프트에러가 발생할 때, 이 에러는 애플리케이션 레이어에서 DCGAN을 이용하여 보상된다. 얼굴 이미지의 소프트에러를 보상하기 위해서 DCGAN 구조를 이용하여 블록 데이터의 손실을 보상한다. 시뮬레이션 결과를 통하여, 제안된 방식이 소프트에러로 인한 성능 악화를 효율적으로 보상한다는 것을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1257-1260
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• 2005

This paper is related to optimization in the image data format, which can make a great effect in performance of data compression and is based on the wavelet transform and JPEG2000. This paper established a criterion to decide the data format to be used in wavelet transform, which is on the bases of the data errors in frequency transform and quantization. This criterion has been used to extract the optimal data format experimentally. The result were (1, 9) of 10-bit fixed-point format for filter coefficients and (9, 7) of 16-bit fixed-point data format for wavelet coefficients and their optimality was confirmed.

• 전자공학회논문지S
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• 제35S권2호
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• pp.106-113
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• 1998

Quantizer with bit rate control performs lossy compressionin moving image coding. Efficient quantizer can improve subjective quality of reconstructed image at the same bit rate because most of errors are occured at this stage. Although quantization matix of current compression stantards reflects human visual system, the performance of their quantization matrixes is not always optimal because they are not considering each image characteristics. We proposed a new adaptive optimal quantization matrix obtained by considering complexity of each image subblocks. It resulted in improvments of image quality about 0.05-0.82 dB and good subject quality at edge regions when we simulated the quantization method in various coding statndards.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of the Optical Society of Korea
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• 제20권4호
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• pp.451-463
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• 2016

The misalignment errors and fluctuations in irradiance due to atmospheric turbulence can severely degrade the performance of free-space optical (FSO) systems. In this paper, we investigate the asymptotic bit error rate (BER) performance and diversity orders of FSO links using parallel transmit-diversity schemes. The BER expressions of FSO links with the switch-and-examine transmit (SET), switch-and-examine transmit with post-selection (SETps), dual-branch transmit laser selection (Dual-TLS), and group transmit laser selection (Group-TLS) schemes are derived, based on an approximate channel model. Then numerical simulations for these four schemes in the region of high average signal-to-noise ratio (SNR) are presented under different channel conditions. The results show that the four transmit-diversity schemes can reduce system complexity and overcome the limitation of peak power, without much BER deterioration.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• 전자공학회논문지B
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• 제30B권4호
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• pp.130-137
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• 1993

In this paper, A progressive coding of mean difference pyramid by Hadamard transform of the difference between two successive pyramid levels has been studied. A block adaptive bit allocation method based on ac energy of each sub-block has been proposed, which efficiently reduces the final distortion in the progressive transmission of image parameters. In our scheme, the dc energy equals the sum of the quantization errors of the Hadamard transform coefficients at previous level. Therefore proposed allocation method includes the estimation of dc energy at each pyramid level. Computer simulation results show some improvements in terms of MSE and picture quality over the conventional fixed allocation scheme.