• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.7-12
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• 2008

In this study, the wide width effect that the increasing rate of drain current and the value of cutoff frequency decrease with larger finger number is observed. For modeling this effect, an improved SPICE MOSFET RF model that finger number-independent external source resistance is connected to a conventional BSIM3v3 RF model is developed. Better agreement between simulated and measured drain current and cutoff frequency at different finger number is obtained for the improved model than the conventional one, verifying the accuracy of the improved model for $0.13{\mu}m$ multi-finger MOSFET.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.671-674
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• 2005

The series parasitic resistances ($R_s$, $R_g$, $R_d$, $R_{sub}$) of BSIM3v3 RF MOSFET macro model were directly extracted from measured S-parameters in the GHz region by using simple 2-port parameter equations. Also, overlap capacitance and junction capacitance parameters were extracted by tuning $S_{11}$, $S_{12}$, and $S_{22}$ respectively while DC-parameters and all parasitic resistances are fixed at previously extracted values. These data are verified to be accurate by observing good correspondence between modeled and measured S-parameters up to 10GHz.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.675-678
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• 2005

An improved BSIM3v3 RF Macro model with RC parallel substrate circuit has been developed to simulate RF characteristics of the output admittance in MOSFET accurately. This improved model shows better agreements with measured $Y_{22}-parameter$ up to 10 GHz than conventional one with a single substrate resistance, verifying the accuracy of the improved one.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.545-546
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• 2006

The improved model that external capacitances are connected to a conventional BSIM3v3 RF Macro model with Rg and Rsub is developed in this paper. The extracted external capacitances and resistances are modeled by scalable fitting equations. The modeled S-parameters of $0.13{\mu}m$ NMOSFET agree well with measured ones from 10MHz to 10GHz, verifying the accuracy of the improved model.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.2
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• pp.8-13
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• 1999

In this paper, an analytical threshold voltage model is proposed by replacing the conventional GCA(Gradual Channel Approximation) with the assumption that a normal depletion layer width in the intrinsic region will vary quasi-linearly according to the channel direction. Derived threshold voltage expression is written as a function of the effective channel length, drain voltage, substrate bias voltage, substrate doping concentration, and the oxide thickness. Calculated results show almost similar trends with BSIM3v3's results in a satisfactory accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.555-559
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• 2003

In this paper, a new CMOS RF model for RF IC design including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for tile first time for accurately predicting the RF behavior of CMOS devices. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled with a parallel branch added in equivalent circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3. the proposed RF model shows good agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.