• 전기화학회지
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• 제2권3호
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• pp.138-143
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• 1999

최근 large scale integrated circuits(LSI) 및 printed circuit board(PCB)의 세밀화가 전자기기의 소형화로 인하여 필수 불가결하게 되었다. 전해 도금은 LSI및 PCB의 전도도 및 부식저항을 향상시키기 위해서 전도성 라인의 말단에 적용되고 있다. 그러나 회로 기판의 소형화 및 고직접화로 인하여 적용되지 못하고 있다. 따라서 최근 무전해 도금은 복잡한 장치와 외부에서 전원을 필요치 않는 작동의 간편함 때문에 매우 각광 받고 있는 방법 중의 하나이다. 본 연구는 무전해 니켈/금도금의 도금 기술 개발을 위해 시험하였다. 무전해 니켈 도금은 $85^{\circ}C$의 도금 욕에서 PCB기판 위에 침적 시켰고 그 다음 금층은 동일한 방법으로 $90^{\circ}C$에서 니켈 층위에 침적 시켰다. Bonderbility는 무전해 니켈/금도금의 안정성을 평가하기 위해 gold wire 또는 solder ball 테스트로 실험하였다.

• Journal of Magnetics
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• 제14권2호
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• pp.53-61
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• 2009

Herein, different concepts for domain wall propagation based on currents and fields that could potentially be used in magnetic data storage devices based on domains and domain walls are reviewed. By direct imaging, we show that vortex and transverse walls can be displaced using currents due to the spin transfer torque effect. For the case of field-induced wall motion, particular attention is paid to the influence of localized fields and local heating on the depinning and propagation of domain walls. Using an Au nanowire adjacent to a permalloy structure with a domain wall, the depinning field of the wall, when current pulses are injected into the Au nanowire, was studied. The current pulse drastically modified the depinning field, which depended on the interplay between the externally applied field direction and polarity of the current, leading subsequently to an Oersted field and heating of the permalloy at the interface with the Au wire. Placing the domain wall at various distances from the Au wire and studying different wall propagation directions, the range of Joule heating and Oersted field was determined; both effects could be separated. Approaches beyond conventional field- and current-induced wall displacement are briefly discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.4-4
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• 2009

Surface analysis on defective wire-bonding pads are performed in flash memory assembly. Week wire bonding may cause a significant effect on the final product reliability, and the surface condition of the aluminum bond pads is critical in terms of product reliability. To find out possible week bonding on semiconductor interconnects, ball sheer test (BST) has been performed. On some defective or week bonded pads, we have investigated the surface contents, assuming that the week bonding is induced from the surface conditions. AES and XPS are employed for the quantitative surface analysis on defective dies.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2002년도 금형가공 심포지엄
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• pp.225-230
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• 2002

As in most metal forming processes, die and lubrication are of vital importance in hydrostatic extrusion. An efficient die design and lubrication system selection reduce the pressure required for a given reduction ratio by lowering friction at the billet-die interface. In contrast to the conventional macroscopic extrusion, fine-wire fabrication requires higher extrusion pressure and effect of friction is much more significant. Forming fine Au, Ag, and Cu wire with hydrostatic extrusion process in cold condition, the effect of extrusion die angle, lubrication and billet's initial diameter was studied.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.1-6
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• 2014

고출력 LED 패키지의 열적 경로(thermal path)를 줄이기 위해 플립칩 본딩법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 Au-Sn 열압착 본딩 및 Sn-Ag-Cu(SAC) 리플로우 본딩을 이용하여 본딩 특성 및 열적특성을 비교 평가 하였다. Au-Sn 열압착 본딩은 50 N에서 $300^{\circ}C$의 접합온도로 본딩하였고, SAC 솔더는 솔더페이스트를 인쇄한 후 리플로우법으로 피크온도 $255^{\circ}C$에서 30 sec에서 본딩하였다. SAC 솔더를 사용한 LED 패키지의 전단강도는 $5798.5gf/mm^2$로 Au-Sn 열압착 본딩의 $3508.5gf/mm^2$에 비해 1.6배 높았다. 파단면과 단면분석 결과 Au-Sn, SAC 솔더 모두 LED 칩 내부에서 파단이 일어나는 것을 관찰하였다. 반면 Au-Sn 열압착 본딩 샘플의 열저항은 SAC솔더 접합 샘플에 비해 낮았으며, SAC 솔더 접합부 내부의 기공에 의해 열저항이 커짐을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 센서 박막재료 반도체재료 기술교육
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• pp.86-89
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• 2002

We give pressure stimulation into organic thin films and then manufacture a device under the accumulation condition that the state surface pressure is 10[mN/m]. In processing of a device manufacture, we can see the process is good from the change of a surface pressure for organic thin films and transfer ratio of area per molecule. The structure of manufactured device is Au/Poly-${\gamma}$ Benzyl $_D$-Glutamate/Al and Au/Poly-${\gamma}$ Benzyl $_D$-Glutamate/Au; the number of accumulated layers is 1, 3, 5 and 7. Also, we then examined of the MIM device by means of I-V. The I-V characteristic of the device is measured from 0 to +2[V]. We determined electrochemical measurement by using cyclic voltammetry with a three-electrode system. LB film accumulated by monolayer on an ITO. In the cyclicvoltammetry, An Ag/AgCl reference electrode, a platinum wire counter electrode and LB film-coated ITO working electrode measured in $LiBF_4$ solution, stable up to 0.9V vs. Ag/AgCl.

• 한국표면공학회지
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• 제29권6호
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• pp.714-719
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• 1996

For the fabrication of the circuits, contact or terminal areas are usually coated with nickel and gold. Usually, diluted palladium solution is applied to initiate electroless nickel plating on the copper circuits. However, the trace amounts of palladium remains on the resin and it causes the extraneous deposition. We confirmed that selectivity was greatly improved by the treatment with the strong reducing agents such as SBH or DMAB. Bondability was greatly influenced by the contents of phosphorus in the deposited nickel. Stabilizers in the electroless gold plating were also influenced the bonding strength. The baths containing cupferron or potassium nickel cyanide as a stabilizer showed superior bondability. The gold deposits having strong orientation with Au(220) and Au(311) showed good bond ability.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2012년도 춘계학술발표회 논문집
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• pp.135-135
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• 2012

세계 환경유해물질 규제에 대응하여 반도체 substrate의 Pb-free solution의 일환으로 등장한 PPF (Pre-Plated Frame)는 패키지공정 조립성은 물론, 자동차 반도체와 같은 고 신뢰성 및 low cost 요구를 만족하기 위해 초박막 고품질의 도금층과 Sub-micro scale의 rough treatment 와 같은 미세 표면제어 기술, 그리고 Au wire로부터 Cu wire 로의 전환에 대응하는 최적화된 도금층 구조로 발전하고 있다. 이러한 기술적인 진화를 거듭해온 이 기술은 다양한 반도체 substrate에 광범위하게 사용될 수 있기 때문에 향후 PPF기술의 활용저변은 더욱 확대될 전망이다.