• Journal of Institute of Control, Robotics and Systems
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• v.21 no.12
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• pp.1115-1121
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• 2015

Fast inspection of solder ball bumps in ball grid array (BGA) is an important issue in the flip chip bonding technology. Particularly, semiconductor industry has required faster and more accurate inspection of micron-size solder bumps in flip chip bonding, as the density of balls increase dramatically. In this paper, we describe an inspection approach of BGA balls by using 5-step ring illumination device and normalized cross-correlation (NCC) method. The images of BGA ball by the illumination device show unique and distinguishable characteristic contours by their 3-D shapes, which are called as "iso-slope contours". Template images of reference ball samples can be produced artificially by the hybrid reflectance model and 3D data of balls. NCC values between test and template samples are very robust and reliable under well-structured condition. The 200 samples on real wafer are tested and show good practical feasibility of the proposed method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.103-107
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• 2009

In this paper, we designed and implemented a dual band chip antenna for WLAN, which contains within the small LAN card contrary to the enternal AP(Access Point) antenna. Limiting about the antenna size, we used dielectrics of high permittivity. Totally considering problems of demand-supply, price and characteristics, we used that relative dielectrics of ceramic is 9.8 and the thickness is 3.5mm and 5mm. Ceramic antenna can be used not only triple mode of IEEE 802.11.a,g and b but also broadband. The frequency bands have wideband characteristics of 2.4~2.5GHz and 4.9~5.85GHz and relatively constant performance.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1680-1681
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• 2011

In this paper, particle counting system using a CMOS image sensor is demonstrated. The system utilizes a linear photodetector array as a detection element. Therefore, the particles are detected by large detection region, in contrast to a single detector in conventional particle counting devices, while maintaining the sensitivity. The advantage of proposed system is that particles are detected in a relatively large area without using the particle focusing method. Also, proposed system can be easily integrated with a microfluidic chip by attaching the device underneath the bottom plate of the microfluidic chip. Detection of polystyrene microbeads has been tested at a flow rate of 4.89mm/s. For 21 measurements, proposed system showed an average count error of 7.29% and a standard deviation of 4.74%. Potentially, the proposed system can detect even smaller particles simply by utilizing a higher resolution CMOS image sensor.

• Journal of Mechanical Science and Technology
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• v.14 no.3
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• pp.350-357
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• 2000

Experiments were performed by using PF-5060 and water to investigate the influence of an aspect ratio of a horizontal rectangular channel on the cooling characteristics from an in-line $6{\times}1$ array of discrete heat sources which were flush mounted on the top wall of the channel. The experimental parameters were aspect ratio of rectangular channel, heat flux of simulated VLSI chip, and channel Reynolds number. The chip surface temperatures decreased with the aspect ratio at the first and sixth rows, and decreased more rapidly at a high heat flux than at a low heat flux. The measured friction factors at each aspect ratio for both water and PF-5060 gave a good agreement with the values predicted by the modified Blasius equation within ${\pm}7%$. The Nusselt number increased as the aspect ratio decreased, but the increasing rate of Nusselt number reduced as the aspect ratio decreased. A 5:1 rectangular channel yields the most efficient cooling performance when the heat transfer and pressure drop in the test section were considered simultaneously.

• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Design & Manufacturing
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• v.10 no.3
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• pp.1-7
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• 2016

In the semiconductor industry the memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. After injection molding process the side gates were needed to remove for further assembly process. ln this study, the cold press cutting process was applied to remove the gates. For design of punch and die, the cold press cutting analysis was implemented by$DEFORM-2D^{TM}$ ln consideration of the simulation results, an adequate punch and die was designed and made for the cutting unit. In order to verify the performance of cutting process, the roughness of cutting section of the part was measured and was satisfied in requirement.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.11
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• pp.960-967
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• 2013

Shape recognition of solder ball bumps in a BGA (Ball Grid Array) is an important issue in flip chip bonding technology. In particular, the semiconductor industry has required faster and more accurate inspection of micron-size solder bumps in flip chip bonding as the density of balls has increased dramatically. The difficulty of this issue comes from specular reflection on the metal ball. Shape recognition of a metal ball is a very realproblem for computer vision systems. Specular reflection of the metal ball appears, disappears, or changes its image abruptly due to tiny movementson behalf of the viewer. This paper presents a practical shape recognition method for three dimensional (3-D) inspection of a BGA using a 5-step ring illumination device. When the ring light illuminates the balls, distinctive specularity images of the balls, which are referred to as "iso-slope contours" in this paper, are shown. By using a mathematical reflectance model, we can drive the 3-D shape information of the ball in aquantitative manner. The experimental results show the usefulness of the method for industrial application in terms of time and accuracy.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.