• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
• /
• pp.2367-2370
• /
• 2003

A fast pattern classification algorithm with Cellular Parallel Processing Network-based dynamic programming is proposed. The Cellular Parallel Processing Networks is an analog parallel processing architecture and the dynamic programming is an efficient computation algorithm for optimization problem. Combining merits of these two technologies, fast Pattern classification with optimization is formed. On such CPPN-based dynamic programming, if exemplars and test patterns are presented as the goals and the start positions, respectively, the optimal paths from test patterns to their closest exemplars are found. Such paths are utilized as aggregating keys for the classification. The pattern classification is performed well regardless of degree of the nonlinearity in class borders.

• 대한전자공학회논문지
• /
• 제27권1호
• /
• pp.10-19
• /
• 1990

A fault tolerant control system, in which a digital back-up controller system is added on the existing analog control system, is developed for enhancing reliability of boiler control system in power plant. The digital back-up controller system(DBCS) has a multi-processor structure with capabilities of fault diagnosis, back-up control, self test, and graphic monitoring. Specifically, switching mechanism composed of expandable modules is designed so that back-up controller takes over any faulty control loops and the number of back-up control loops is determined as that of simultaneous faults. A process simulator that simulates the boiler analog control system is developed for safety test and performance evaluation prior to real plant application. DBCS is installed at the Ulsan thermal power plant, and fault tolerant control performance is assured under the faults that some controller modules are pulled out.

• 반도체디스플레이기술학회지
• /
• 제3권1호
• /
• pp.1-7
• /
• 2004

In this paper, we have developed the DC parameters test system which inspects the properties of DC parameters for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC(Analog-to-Digital Converter), DAC(Digital-to-Analog Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. In the comparison of results, the results of the simulation are very similar to the ones of the implementation.

• ETRI Journal
• /
• 제36권6호
• /
• pp.894-904
• /
• 2014

Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4 400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.

• ETRI Journal
• /
• 제30권4호
• /
• pp.546-554
• /
• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
• /
• pp.865-868
• /
• 1993

This paper describes a simple random signal generator employing by CMOS analog technology in current mode. The system is a nonlinear dynamical system described by a difference equation, such as x(t＋1) = f(x(t)) , t = 0,1,2, ... , where f($.$) is a nonlinear function of x(f). The tent map is used as a nonlinear function to produce the random signals with the uniform distribution. The prototype is implemented by using transistor array devices fabricated in a mass product line. It can be easily realized on a chip. Uniform randomness of the signal is examined by the serial correlation test and the $\chi$2 test.

• 한국압력기기공학회 논문집
• /
• 제20권1호
• /
• pp.7-15
• /
• 2024

Environmental qualification is required for safety related electrical equipment under harsh environments located in nuclear power plants according to 10 CFR 50.49 and RG 1.89. As analog technology has recently been replaced by digital technology, NRC established RG 1.209 as a regulatory guideline for environmental qualification of safety related computer-based I&C system located in mild environments, requiring evaluation for electromagnetic compatibility, smoke exposure and type test for actual service conditions such as temperature and humidity. In this paper, the trend of environmental qualification for digital equipment is analyzed by comparing the environmental qualification requirements between digital and analog equipment.

• Journal of information and communication convergence engineering
• /
• 제6권1호
• /
• pp.43-46
• /
• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• Journal of Acupuncture Research
• /
• 제21권5호
• /
• pp.27-44
• /
• 2004

Objective : To evaluate the pain improvement of the lumbago patients taken the electro-acupuncture therapy using Visual Analogue Scale. Methods : The 25 patients of 46 lumbago patients visited department of Acupuncture & Moxibustion in National Medical Center from 1st March to 20th August had taken the electro-acupucture therapy more than 5 times. We checked on their age, sex, onset, radiating pain, back pain past history and Straight Leg Raising test. And we evaluated their improvement of back pain using Visual Analog Scale(VAS) at each visit. Then we analyzed the pain improvement by their age, sex, onset, radiating pain, back pain past history, Straight Leg Raising test, visiting frequency and Visual Analog Scale on 1st visit(VAS1) Results : VAS of 24 patients has improved and VAS of one patient has not been changed. There's no patient getting worse. The women and the positive group at SLR Test had better result of pain improvement. Conclusion : The lumbago patients taken electro-acupuncture more than 5 times showed significantly different pattern of pain improvement according to the sex and the SLR test.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권5호
• /
• pp.713-718
• /
• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.