• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.334-340
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• 2006

A compact biosignal monitoring device was developed. Electrodes for electrocardiogram (ECG) and a LED and silicon detector for photoplethysmogram (PPG) were used. A lead II type was arranged for ECG measurement and reflected light was measured at the finger tip for PPG. A single chip microprocessor (model ADuC812, Analog Device) controlled a measurement protocol and processed measured signals. PPG and ECG had a sampling rate of 300 Hz with 8-bit resolution. The maximum power consumption was 100 mW. The microprocessor computed pulse transit time (PTT) between the R-wave of ECG and the peak of PPG. To increase the resolution of PTT, analog peak detectors obtained the peaks of ECG and PPG whose interval was calculated using an internal clock cycle of 921.6 kHz. The device was designed to be operated by 3-volt battery. Biosignals can be measured for $2{\sim}3$ days continuously without the external interruptions and data is stored to an on-board memory. Our system was successfully tested with human subjects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• Journal of Radiation Protection and Research
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• v.12 no.1
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• pp.12-25
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• 1987

A basic multichannel analyser (MCA) system have been designed and constructed with the successive approximation type ADC (Analog to Digital Converter). Linear Gate, window, and palse stretcher consist of mainly linear and logic IC's, and are properly combined together to achieve short dead time and good linearity of the system. ADC 1211 (analysing time: $120{\mu}sec$) and S-RAM (static random acess memory) 6264 are used in ADC module. Two 6264 memories are connected in parallel in order to-provide enough counting capacity ($2^{16}-1$). Interfaced microcomputer Apple II controls this system and analizes the counted data. The system is tested by input pulses between 0V to 10V from oscillator.

• Smart Media Journal
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• v.2 no.1
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• pp.42-47
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• 2013

The paper presents VDR system for efficiency of ocean navigation device and how to output and to save data using this system as well as compressed digital data and analog video output from the camera are utilized at the same time. The compressed digital data is used to store video for VDR device while analog video is used to display on screen in real-time so that VDR system saves the load on SD memory card without navigation terminal and output it with real-time video. Also, the control method using VDR system are proposed for saving and outputting data.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.661-673
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• 2010

This paper presents recent developments in an extremely compact, wireless impedance sensor node (the WID3, $\underline{W}$ireless $\underline{I}$mpedance $\underline{D}$evice) for use in high-frequency impedance-based structural health monitoring (SHM), sensor diagnostics and validation, and low-frequency (< ~1 kHz) vibration data acquisition. The WID3 is equipped with an impedance chip that can resolve measurements up to 100 kHz, a frequency range ideal for many SHM applications. An integrated set of multiplexers allows the end user to monitor seven piezoelectric sensors from a single sensor node. The WID3 combines on-board processing using a microcontroller, data storage using flash memory, wireless communications capabilities, and a series of internal and external triggering options into a single package to realize a truly comprehensive, self-contained wireless active-sensor node for SHM applications. Furthermore, we recently extended the capability of this device by implementing low-frequency analog-to-digital and digital-to-analog converters so that the same device can measure structural vibration data. The compact sensor node collects relatively low-frequency acceleration measurements to estimate natural frequencies and operational deflection shapes, as well as relatively high-frequency impedance measurements to detect structural damage. Experimental results with application to SHM, sensor diagnostics and low-frequency vibration data acquisition are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.4
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• pp.9-17
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• 2012

In this paper, we show the memory effect of the high-power amplifiers for wied-band signals, present a compensation method for the nonlinearity combined with memory effect, and analyze its performance. For the modeling and the compensation of the nonlinear high-power amplifier with memory effect, we investigate the Volterra series model, the Wiener model, and the Hammerstein model. As a compensator scheme, we propose a digital feedforward technique. Compared to analog feed-forward scheme, the proposed scheme has better stability and adaptability to the environmental changes. It has a simpler structure than the conventional digital nonlinear compensation schemes. The result of computer simulations using ADS of the Agilent shows that spectral re-growth is suppressed by more than 20 dB, which amounts to at least 10 dB back-off. Considering the compensation performance, implementation complexity, and convergence rate, we could conclude the Wiener model is most suitable for the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.