• Journal of information and communication convergence engineering
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• v.21 no.4
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• pp.337-345
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• 2023

In this study, we formulated a method that evaluates Taekwondo Poomsae performance using a series of choreographed training movements. Despite recent achievements in 3D human pose estimation (HPE) performance, the analysis of human actions remains challenging. In particular, Taekwondo Poomsae action analysis is challenging owing to the absence of time synchronization data and necessity to compare postures, rather than directly relying on joint locations owing to differences in human shapes. To address these challenges, we first decomposed human joint representation into joint rotation (posture) and limb length (body shape), then synchronized a comparison between test and reference pose sequences using DTW (dynamic time warping), and finally compared pose angles for each joint. Experimental results demonstrate that our method successfully synchronizes test action sequences with the reference sequence and reflects a considerable gap in performance between practitioners and professionals. Thus, our method can detect incorrect poses and help practitioners improve accuracy, balance, and speed of movement.

• International Journal of Computer Science & Network Security
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• v.24 no.4
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• pp.1-10
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• 2024

In the era of big data, the growth of e-commerce transactions brings forth both opportunities and risks, including the threat of data theft and fraud. To address these challenges, an automated real-time fraud detection system leveraging machine learning was developed. Four algorithms (Decision Tree, Naïve Bayes, XGBoost, and Neural Network) underwent comparison using a dataset from a clothing website that encompassed both legitimate and fraudulent transactions. The dataset exhibited an imbalance, with 9.3% representing fraud and 90.07% legitimate transactions. Performance evaluation metrics, including Recall, Precision, F1 Score, and AUC ROC, were employed to assess the effectiveness of each algorithm. XGBoost emerged as the top-performing model, achieving an impressive accuracy score of 95.85%. The proposed system proves to be a robust defense mechanism against fraudulent activities in e-commerce, thereby enhancing security and instilling trust in online transactions.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1627-1637
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• 2024

This research paper proposes a novel methodology for predicting the optimal location of friction supports to effectively mitigate vibrational energy in piping systems. The incorporation of friction forces in the dynamic characteristics of the system introduces inherent nonlinearity, making its analysis challenging. Typically, numerical solutions in the time domain are employed to circumvent the complexities associated with finding analytic solutions for nonlinear systems. However, time domain analysis (TDA) can be computationally intensive and demand significant computational resources due to the intricate calculations stemming from nonlinearity. To address this computational burden, this study presents an efficient approach based on linear analysis to predict the ideal position for installing friction supports as a replacement for fixed supports. Furthermore, we investigate the relationship between the installation positions of friction supports and their effectiveness in absorbing vibrations using the harmonic balanced method (HBM). Both methodologies are validated by comparing the obtained results with those obtained through time domain analysis (TDA) using the finite element method (FEM).

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1755-1758
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• 2004

Misfiring is often observed during the high temperature quality assurancetest of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases lime lag in address discharge, and results m increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.6
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• pp.568-572
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• 2009

We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

• Information Systems Review
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• v.4 no.1
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• pp.47-67
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• 2002

Since mid 90's, most of firms utilizing web as a communication vehicle with customers are keenly interested in web log file which contains a lot of trails customers left on the web, such as IP address, reference address, cookie file, duration time, etc. Therefore, an appropriate analysis of the web log file leads to understanding customer's behaviors on the web. Its analysis results can be used as an effective marketing information for locating potential target customers. In this study, we introduced a web mining technique using Clementine of SPSS, and analyzed a set of real web log data file on a certain Internet hub site. We also suggested a process of various strategies build-up based on the web mining results.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.167-180
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• 1996

In the scalar processing oriented machine scalar operations must be performed for the vector processing as many as the number of vector components. So called a vector processing mechanism by the von Neumann operational principle. Accessing vector data hasto beperformed by theevery pointing ofthe instruction or by the address calculation of the ALU, because there is only a program counter(PC) for the sequential counting of the instructions as a memory accessing device. It should be here proposed that an access unit dimensionally to address components has to be designed for the compensation of the organizational hardware defect of the conventional concept. The necessity for the vector structuring has to be implemented in the instruction set and be performed in the mid of the accessing data memory overlapped externally to the data processing unit at the same time.

• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.406-412
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• 2001

IP address lookup is to determine the next hop destination of an incoming packet in the router. The address lookup is a major bottleneck in high performance router due to the increased routing table sizes, increased traffic, higher speed links, and the migration to 128 bits IPv6 addresses. IP lookup time is dependent on data structure of lookup table and search scheme. In this paper, we propose a new approach to build a lookup table that satisfies the memory constraint. The design of lookup table is formulated as an optimization problem. The objective is to minimize average depth from the root node for lookup. We assume that the frequencies with which prefixes are accessed are known and the data structure is level compressed trie with branching factor $\kappa$ at the root and binary at all other nodes. Thus, the problem is to determine the branching factor k at the root node such that the average depth is minimized. A heuristic procedure is proposed to solve the problem. Experimental results show that the lookup table based on the proposed heuristic has better average and the worst-case depth for lookup.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.3 no.1
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• pp.15-24
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• 2004

'The delay and control overhead during route discovery for destinations outside ad hoc networks are major obstacle to achieving scalability in the Internet. To solve this issue, we propose a novel route discovery scheme equipped with two augmented functions. In this paper, the Internet gateway maintains an address cache of Internet nodes frequently accessed from the ad hoc network and replies with an extended Route Response (RREP) message to the Route Request (RREQ) message based on its routing table and the address cache called EXIT(EXternal node Information Table). These augmented functions make the source node determine the location of the destination as fast as possible. Through simulations, the proposed route discovery scheme using both EXIT and extended RREP message shows considerable' reduction in both route discovery time and control message overhead.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.