• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.174-178
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• 2013

A modified driving waveform is proposed to improve the address discharge characteristics using wall charge on the common electrodes in plasma display panel. In the driving scheme of plasma display, after a reset period, the negative charge are accumulated on two front electrodes and positive wall charge are accumulated on the address electrode. As the address discharge during an address period is produced when the scan and address pulses are applied at the same time, negative charge on the scan electrodes and positive charge on the address electrodes are mainly used. On the other hand, as the voltage are only maintained without applying the waveform during an address period on the common electrodes, the wall charge is not used on the common electrodes. In this paper, the address discharge characteristics are investigated with changing pulse applying time and applied voltage amplitude on the common electrodes and consequently the producing time of an address discharge are shortened about 200 ns compared with the conventional driving waveform.

• Journal of architectural history
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• v.20 no.1
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• pp.7-22
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• 2011

This paper deals with a fundamental study for '$Tonhobeondo$統戶番圖-making' of Hanseongbu(modern Seoul) before the Japanese colonial period. '$Tonhobeondo$統戶番圖-making' will be accomplished through analysis on Kwangmu-census光武戶籍 as a map of address-system in the Joseon period. It is possible to consider the urban changes of Hanseongbu(modern Seoul) because of '$Tonhobeondo$統戶番圖' reflects a urban situation from the 1897 to 1906. At present, an address-system of Korea was made by the cadastral survey in the 1914. By the way, new address-system was a completely different from traditional address-system of Joseon period. Consequently, different two address-system caused a lot of difficulties the study on the urban changes. For such a reason '$Tonhobeondo$統戶番圖-making' is very important. If '$Tonhobeondo$統戶番圖-making' would be accomplished, it will be used by a field of urban, architectural and historical science study besides.

• Journal of Information Display
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• v.2 no.1
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• pp.24-33
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• 2001

The characteristics of the reset and the address discharges of an alternating current Plasma Display Panel (ac PDP) were studied using 2-dimensional numerical discharge cell simulation. We investigated the wall charge variations during the reset discharge adopting ramping reset pulse and the subsequent addressing discharge. The roles of the ramping reset scheme can be divided into two stages, each electrode gathers wall charges during ramping-up of the initial stage and the built-up wall charges are lost during ramping-down of the later stage. Address discharge does not only change the wall charge distributions on the address and the scan electrodes but also on the sustain electrode. The increase in the wall charges on the sustain electrode was observed with the variation of the applied voltage to the sustain electrode during the address period. The increase of the applied voltage to the sustain electrode during the address period is expected to induce the decrease of the sustain voltage during the display period.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.8
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• pp.407-414
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• 2004

In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.647-650
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• 2005

A new driving scheme, Address and Display Period Complex Driving for Expanding Gray Scale(ACE), is proposed by mixing Address Display period Separated(ADS) and Address While Display(AWD). In this method scan lines are divided in blocks driving by AWD and scan lines in block progress sequential high speed addressing. ADS driving get accomplished in low gray level for expanding gray scale. Scan time is reduced and the number of subfields is increased by high speed addressing of ACE. That expands the gray scale and decreases the dynamic false contour. Also, that improves contrast by using ramp reset.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.135-139
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• 2015

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.726-729
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• 2003

A new driving method is proposed to reduce the address period. The scan time of new driving method overlaps with the next scan time during the discharge lag time. Thus, without reducing the address pulse width and the scan pulse width, the new addressing method can reduce the address period. The results show that the scan time of about 100ns ${\sim}$ 300ns can be overlapped without the misfiring,.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1830-1833
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• 2002

We measured 3-dimensional temporal behavior of the light emitted from AC plasma display panel(PDP) at various auxiliary voltage pulse width supplied to the address electrode in sustain period using scanned point detecting system. In the case of applying an auxiliary address voltage pulse, the light emission starts at the inner edges of the cathode so the larger discharge volume toward address electrode can be obtained compared with the normal sustain discharge. Especially, when the auxiliary voltage pulse width is the $2{\mu}s$, the maximum luminance and long emission time can be obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1258-1261
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• 2005

The ramp type bias voltage applied to the common electrode during a reset-period is newly proposed to lower the background luminance and to improve the address discharge characteristics in AC-PDP. The positive ramp bias voltage is applied during the ramp-up period, whereas the negative ramp bias voltage is applied during the ramp-down period. The effects of the voltage slopes in both the positive and negative ramp bias voltages on the background luminance and address voltage characteristics are examined intensively. It is observed that the optimized positive and negative ramp bias voltages applied to the common electrode during the ramp-period can lower the background luminance and also enhance the address discharge characteristics of the AC-PDP.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.503-506
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• 2004

In this paper, we suggest a new driving waveform for stable address discharge in AC PDP without the reduction of contrast ratio. To analyze the influence of cross-talk between discharge and non-discharge cells and verify that proposed waveform shows a stable address discharge, we measured the address discharge delay time. The proposed waveform shows the reduction of the cross-talk and concurrently the improvement of address voltage margin compared with those of selective reset waveform having one reset period in 1TV-Field..