• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.535-541
• /
• 2016

A low phase noise META-VCO based-on meta-structure was designed using 65 nm CMOS process. We used a meta-structure to get good phase noise characteristics. The measured phase noises are -67.8 dBc/Hz, -96.37 dBc/Hz, and -107.37 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset respectively. The META-VCO operates 8.45~8.77 GHz according to VCTRL, and the output power is -19.12 dBm. The power consumption is 28 mW with 1.2-V supply voltage. The calculated FOM is -140.76 dBc/Hz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.817-824
• /
• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Journal of electromagnetic engineering and science
• /
• v.18 no.2
• /
• pp.141-143
• /
• 2018

Two 110-GHz oscillators have been developed in 65-nm CMOS technology. To study the effect of layout on the circuit performance, both oscillators had the same LC cross-coupled topology but different layout schemes of the circuit. The oscillator with the conventional cross-coupled design (OSC1), showed an output power of -3.9 dBm at 111 GHz with a phase noise of -75 dBc/Hz at 1-MHz offset. On the other hand, OSC2, with a modified cross-coupled line layout, generated an output power of -2.0 dBm at 117 GHz with a phase noise of -77 dBc/Hz at 1-MHz offset. The result indicates that the optimized layout can improve key oscillator performances such as oscillation frequency and output power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.12
• /
• pp.1236-1242
• /
• 2014

In this work, a D-band VCO(Voltage Controlled Oscillator) has been developed in a 65-nm CMOS technology. The circuit was designed based on push-push mechanism. The output oscillation frequency of the fabricated VCO varied from 152.7 GHz to 165.8 GHz, and the measured output power was from -17.3 dBm to -8.7 dBm. A phase noise of -90.9 dBc/Hz is achieved at 10 MHz offset. The chip size of the circuit is $470{\mu}m{\times}360{\mu}m$ including the probing pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.10
• /
• pp.877-882
• /
• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.7
• /
• pp.784-790
• /
• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.10
• /
• pp.1151-1156
• /
• 2012

In this paper, the baseband filter is proposed in order to maintain a constant sensitivity regardless of distances for 77 GHz automotive radar system. Using existing DCOC loop circuit can remove DC offset and also cancel differences of received power depending on the distance. Measured results show that the maximum gain is 51 dB and high pass cutoff frequency can be tuned from 5 kHz to 15 kHz. The slope of high pass filter can be tuned from -10 to -40 dB/decade for the distance compensation. The measured NF and IIP3 are 26 dB and +4.5 dBm with 4.3 mA at 1.0 V supply voltage, respectively. The fabricated die size $500{\mu}m{\times}1,050{\mu}m$ excluding the in/out pads.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.133-138
• /
• 2021

We propose a Ku-band three-stack CMOS power amplifier to enhance the output power and efficiency. To minimize the dc power consumption, the driver stage is designed using common-source structure. To obtain high output power and utilize a voltage combining method, the power stage is designed using stack structure. To verify the proposed power amplifier structure, we design a Ku-band power amplifier using 65-nm RFCMOS process which provide nine metal layers. The P1dB, power-added efficiency, and gain are higher than 20 dBm, 23 dB, and 25%, respectively, while the operating frequency is 14 GHz-16 GHz.

• Journal of the Optical Society of Korea
• /
• v.18 no.5
• /
• pp.564-568
• /
• 2014

We present a 25-Gb/s optical transmitter composed of a Si ring modulator and CMOS driver circuit. The Si ring modulator is realized with 220-nm Si-on-insulator process and the driver circuit with 65-nm CMOS process. The modulator and the driver are hybrid-integrated on the printed circuit board with bonding wires. The driver is designed so that the parasitic bonding wire inductance provides enhanced driver bandwidth. The transmitter successfully demonstrates 25-Gb/s operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.99-106
• /
• 2012

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.