JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

  • Li, Jing (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Ning, Ning (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Du, Ling (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Yu, Qi (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Liu, Yang (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China)
  • Received : 2011.08.29
  • Published : 2012.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

Keywords

References

  1. Rafael J. Betancourt-Zamora, Thomas H. Lee, "Low phase noise CMOS ring oscillator VCOs for frequency synthesis," 2nd International Workshop on Design of Mixed-Mode Integrated Circuits, pp.37-40, Jul., 1998.
  2. B. Razavi, "The Role of PLLs in Future Wireline Transmitters," Circuits and Systems I, IEEE Transactions on, Vol.56, No.8, pp.1786-1793, Aug., 2009. https://doi.org/10.1109/TCSI.2009.2027507
  3. Jung-Sheng Chen and Ming-Dou Ker, "Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology," Electron Devices, IEEE Transactions on, Vol.56, No.8, pp.1774-1779, Aug., 2009. https://doi.org/10.1109/TED.2009.2022696
  4. Kadaba R. Lakshmikumar, "Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions," Circuits and Systems II, IEEE Transactions on, Vol.56, No.5, pp.389-393, May, 2009. https://doi.org/10.1109/TCSII.2009.2019171
  5. Todd Charles Weigandt, "Low Phase Noise, Low Timing Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers: [PHD thesis]," University of Califorlia, pp.84-89, 1998.
  6. B. Razavi, "Design of Analog CMOS Integrated Circuits," McGraw-Hill Companies, Forth Edition, 2000.
  7. P.R. Gray and R.G. Meyer, "Analysis and Design of Analog Integrated Circuits," John Wiley and Sons, Forth Edition, 2005.