• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.581-583
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• 2003

현재 인터넷에서는 사용자의 급격만 증가로 인해 고성능의 라우터를 요구하고 있고 주소부족으로 IPv4에서 IPv6로 변화를 하고 있다. IPv4처럼 IPv6에서도 Address Lookup이 병목이 될 것이며 IPv4와는 달리 IPv6는 128bit의 주소 길이를 가지고 있어 이에 맞는 라우터 구조와 Address Lookup 알고리즘이 필요하다. 본 논문에서는 IPv6주소 128bit 중 외부에서 할당받는 64bit를 3단계로 나누는 계층적 네트워크 구성과 각 단계에 적합한 라우팅 테이블 구조와 Address Lookup 알고리즘에 대해 연구하였고 펜티엄 III 866MHz의 프로세서에서 알고리즘의 검색 시간을 측정해 각 단계에 맞는 라우팅 테이블 구조를 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.51-51
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• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.11
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• pp.643-649
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• 2005

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.1-10
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• 1984

The time division multiplexing PCM encoder which is constructed for an airborne telemetering system is investigated. Selected by program switch, the PCM encoder has 0~64 words/framd($\pm$5V full scale) of allowable analog input channels, 0~30bits(5V$\pm$1V or 0V$\pm$1V dc) of discrete channels, 70 and 140K bits/sec of bit rate and 8~12bits/word of resolution. And filtered output PCM code is NRZ-L and Bi-S through the 5 pole Bessel LPF(f=100kHz), and the maximum accuracy of PCM encoder is $\pm$0.2% of its full scale.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.50-59
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• 2000

Stereo vision is a technique extracting depth information from stereo images, which are two images that view an object or a scene from different locations. The most important procedure in stereo vision, which is called stereo matching, is to find the same points in stereo images. It is difficult to match stereo images in real time because stereo matching requires heavy calculation. In this Paper we design a digital VLSI to Process stereo matching in real time, which we call stereo image match processor (SIMP). For implementation of real time stereo matching, sliding memory and minimum selection tree are presented. SIMP is designed with pipeline architecture and parallel processing. SIMP takes 64 gray level 64$\times$64 stereo images and yields 8 level 64 $\times$64 disparity map by 3 bit disparity and 12 bit address outputs. SIMP can process stereo images with process speed of 240 frames/sec.

• Journal of Advanced Navigation Technology
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• v.15 no.5
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• pp.865-870
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• 2011

MD-64 is a 64-bit block cipher suitable for the efficient implementation in hardware environments such as WSN. In this paper, we propose a related-key amplified boomerang attack on the full-round MD-64. The attack on the full-round MD-64 requires $2^{45.5}$ related-key chosen plaintexts and $2^{95}$ MD-64 encryptions. This work is the first known cryptanalytic result on MD-64.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.55-62
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• 2012

KT-64 is a 64-bit block cipher which use CSPNs suitable for the efficient FPGA implementation. In this paper, we propose a related-key amplified boomerang attack on the full-round KT-64. The attack on the full-round KT-64 requires $2^{45.5}$ related-key chosen plaintexts and $2^{65.17}$ KT-64 encryptions. This work is the first known cryptanalytic result on KT-64.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.70-75
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• 2012

LED-64 is a 64-bit block cipher proposed in CHES 2011 and suitable for the efficient implementation in constrained hardware environments such as WSN. In this paper, we propose a differential fault analysis on LED-64. In order to recover the secret key of LED-64, this attack requires only one random nibble fault and an exhaustive search of $2^8$. This work is the first known cryptanalytic result on LED-64.