A Low Power ROM using Charge Recycling and Charge Sharing

전하 재활용과 전하 공유를 이용한 저전력 롬

  • 양병도 (한국과학기술원 전기 및 전자공학) ;
  • 김이섭 (한국과학기술원 전기 및 전자공학)
  • Published : 2003.07.01

Abstract

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

메모리에서의 대부분의 전력은 프리디코더 라인, 워드 라인, 그리고 비트 라인 등과 같은 커패시턴스가 큰 라인들에서 소모된다. 이 라인들에서의 전력 소모를 줄이기 위하여 전하 재활용과 전하 공유를 사용한 세 가지 기법들이 제안되었다. 이 기법들은 전하 재활용 프리디코더(charge recycling predecoder, CRPD), 전하 재활용 워드 라인 디코더(charge recycling word line decoder, CRWD), 그리고 롬을 위한 전하 공유 비트 라인(charge sharing bit line, CSBL)이다. CRPD와 CRWD는 프리디코더 라인과 워드 라인의 전하를 재활용하여 소모 전력을 반으로 줄여주고, 전하 공유 기법을 사용하는 CSBL은 롬 비트라인의 스윙 전압을 낮춤으로써 소모 전력을 크게 줄여준다. CRPD, CRWD, 그리고 CSBL의 소모 전력은 기존의 82%, 72%, 그리고 64%이다. 제안된 세 가지 기법들을 사용하는 전하 재활용 전하 공유 롬(charge recycling and charge sharing ROM, CRCS-ROM)이 0.35㎛ CMOS공정으로 제작되었다. 제작된 8K×16비트 CRCS-ROM의 코어 크기는 0.51㎟이고 3.3V 전원과 100㎒ 동작 주파수에서 8.63㎽ 을 소모하였다.

Keywords

References

  1. Edwin de Angel, Earl E. Swartzlander, Jr. 'Survey of Low Power Techniques for ROMs,' Intermational Symposium on Low Power Electronics and Design, 1997, Pages 7-11 https://doi.org/10.1145/263272.263274
  2. R. Sasagawa, I. Fukushi, M. Hamaminato, S. Kawashima, 'High-speed Cascode Sensing Scheme for 1.0V Contact-programming Mask ROM,' Symposium on VLSI Circuits, 1999, Pages 95-96 https://doi.org/10.1109/VLSIC.1999.797248
  3. M. M. Khellah, M. I. Elmasry, 'Low-Power Design of High-Capacitive CMOS Circuits Using a New Charge Sharing Scheme,' IEEE International Solid-State Circuits Conference, 1999, Pages 286-287 https://doi.org/10.1109/ISSCC.1999.759257
  4. Byung-Do Yang and Lee-Sup Kim, 'A Low Power Charge-Recycling ROM Architecture,' IEEE International Symposium on Circuits and Systems, 2001, Pages 510-513 https://doi.org/10.1109/TVLSI.2003.816138
  5. Byung- Do Yang and Lee-Sup Kim, 'A Low-Power ROM using Charge Recycling and Charge Sharing,' IEEE International Solid-State Circuits Conference, 2002, Pages 108-109
  6. H. Yamauchi, H. Akamatsu, T. Fujita, 'An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's,' IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, April 1995, pages 423-431 https://doi.org/10.1109/4.375962
  7. M. Hiraki, et al, 'Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's,' IEEE Journal of Solid-State Circuits Conference, Vol. 30, No. 4, April 1995, Pages 397-402 https://doi.org/10.1109/4.375959
  8. K.W. Mai, T.Mori, B.S. Amrutur, R. Ho, B.Wilburm, M.A. Horowitz, I. Fukushi, T.Izawa, S. Mitarai, 'Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques,' IEEE Journal of Solid-State Circuits Conference, Vol. 33, No.11, November 1998, Pages 1659-1671 https://doi.org/10.1109/4.726555