• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.