• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.521-522
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• 2008

This paper presents fully integrated low power consumption limiting amplifier. The proposed limiting amplifier is employed folded cascode structure with source degeneration output stage. This proposed structure demands few transconductance than conventional structure. It can be dramatically decrease current consumption. The total power consumption is only $96.5\;{\mu}W$ under a 1.8 V supply voltage in 9.5 dB limited gain condition. It was designed in using $0.18\;{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1283-1293
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• 1996

This paper descries design concepts, structure and charracteristics of personal communications system based on wideband CDMA under developing for general low-tier mobile telecommunications services as the first step of the next generation mobile telecommunications systems that provide timely exchange of various types of information with anyone, from anywhere, at anytime. Also, wedesign a reverse linktransmitter/receiver structure for personal communications system based on wideband CDMA and validata the performance of the designed structure and establish the each parameter via computer simulation. Simulaation results on the effects of reverse link synchronous transmission and the effects of power control and control and channel coding in pedestrian environment for low-tier services are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.