• Journal of Information Display
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• v.7 no.1
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.648-657
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• 1995

정보처리의 다양화, 고속화를 위하여 장래의 집적회로는 다량의 정보를 단시간에 처리하지 않으면 안된다. 종래, 3년에 4배의 고집적화가 실현되어 LSI개발에 기술 견인차의 역할을 하고 있는 DRAM(Dynamic Random Access Memory)은 미세화기술의 한계를 우려하면서도 오히려 개발에 박차를 가하고 있다. 이러한 DRAM의 미세, 대용량화에는 미세가공 기술, 새로운 메모리 셀과 트랜지스터 기술, 새로운 회로 기술, 그 이외에 재료박막기술, Computer aided design/Design automation(CAD/DA) 기술, 검사평가기술 혹은 소형팩키지(package)기술등의 광범위한 기술발전이 뒷받침되어 왔다. 그 중에서 미세가공 기술 및 새로운 트랜지스터 기술과 메모리 셀 기술을 중심으로 개발 동향을 살펴보고 최근에 발표된 1Gbit DRAM의 시제품 기술에 대하여 분석해 보기로 한다.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.38-39
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• 2003

전기적 저항이 낮은 투명 박막 물질은 현재 flat panel display, electroluminescent device, thin film transistor, solar cell 등 여러 분야에서 연구되고 있다. 그 중에서도 특히 ZnO：Ga는 현재 많이 쓰이는 ITO보다 화학적, 열적으로 안정한 상태를 보이는 투명 전도 산화막 물질로써 본 연구에서는 분광타원법을 이용하여 ZnO：Ga의 광학적 특성을 분석하였다. 본 연구를 위한 시료는 온도에 따른 ZnO：Ga／Sapphire 박막, $O_2$의 압력에 따른 ZnO：Ga／Sapphire 박막, Ga의 doping 농도에 따른 ZnO：Ga／Sapphire 박막으로 제작하였으며, 위상변조형 분광타원계(spectroscopic Phase Modulated Ellipsometer, Jobin-Yvon, UVISEL)를 사용하여 측정대역을 0.74 ~ 4.5 eV, 입사각을 70$^{\circ}$로 하여 측정하였다. (중략)

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.266-274
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• 2024

In this paper, we designed a low-area 32-bit PF (Poly-fuse) OTP IP, a non-volatile memory that stores data required for analog circuit trimming and calibration. Since one OTP cell is constructed using two PFs in one select transistor, a 1cell-2bit multibit PF OTP cell that can program 2bits of data is proposed. The bitcell size of the proposed 1cell-2bit PF OTP cell is 1/2 of 12.69㎛ × 3.48㎛ (=44.161㎛2), reducing the cell area by 33% compared to that of the existing PF OTP cell. In addition, in this paper, a new 1 row × 32 column cell array circuit and core circuit (WL driving circuit, BL driving circuit, BL switch circuit, and DL sense amplifier circuit) are proposed to meet the operation of the proposed multbit cell. The layout size of the 32bit OTP IP using the proposed multibit cell is 238.47㎛ × 156.52㎛ (=0.0373㎛2) is reduced by about 33% compared that of the existing 32bit PF OTP IP using a single bitcell, which is 386.87㎛ × 144.87㎛ (=0.056㎛2). The 32-bit PF OTP IP, designed with 10 years of data retention time in mind, is designed with a minimum programmed PF sensing resistance of 10.5㏀ in the detection read mode and of 5.3 ㏀ in the read mode, respectively, as a result of post-layout simulation of the test chip.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.67-78
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• 1984

EAROM device is an n-channel MOS transistor with a control gate stack ed on the floating gate. On account of channel injection type, channel lengths are designed 4-8 $\mu$m and chinnel widths 5-14 $\mu$m. These devices which have fourstructures of different type control gate are designed by NMOS 5 $\mu$m design rule and fabricated by double polysilicon gate NMOS Process. Double ion implantation is applied to increase punchthrough voltage and gate-controlled channel breakdown voltage. The drain and gate voltage for programming was 13-17V and 20-25V, respectively. EPROM cell fabricated could be erased not by optical method but by electrical method. The result of charge retention test showed decrease in stored charges by 4% after 200 hours at 1$25^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.43-49
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• 2000

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.178-180
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• 2017

This study presents a 2-20 GHz monolithic distributed power amplifier (DPA) using a $0.25{\mu}m$ AlGaN/GaN on SiC high electron mobility transistor (HEMT) technology. The gate width of the HEMT was selected after considering the input capacitance of the unit cell that guarantees decade bandwidth. To achieve high output power using small transistors, a 12-stage DPA was designed with a non-uniform drain line impedance to provide optimal output power matching. The maximum operating frequency of the proposed DPA is above 20 GHz, which is higher than those of other DPAs manufactured with the same gate-length process. The measured output power and power-added efficiency of the DPA monolithic microwave integrated circuit (MMIC) are 35.3-38.6 dBm and 11.4%-31%, respectively, for 2-20 GHz.

• Journal of the Korean Chemical Society
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• v.60 no.3
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• pp.194-202
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• 2016

Two conjugated semiconducting copolymers consisting of 4,7-bis(4-(2-ethylhexyl)-2-thiophene)-2,1,3-benzothiadiazole (DTBT) and benzo[1,2-b:4,5-b']dithiophene with 5-(2-ethylhexyl)-2,2'-bithiophene (BDTBT) or 5-(2-ethylhexylthio)- 2,2'-bithiophene (BDTBT-S) were designed and synthesized as donor materials for organic photovoltaic cells (OPVs). Alkylthio-substituted PBDTBT-S-DTBT showed a higher hole mobility and lower highest occupied molecular orbital (HOMO) energy level (by 0.08 eV) than the corresponding alkyl-substituted PBDTBT-DTBT. An OPV fabricated using PBDTBT-S-DTBT showed higher V_OC and J_SC values of 0.83 V and 7.56 mA/cm², respectively, than those of a device fabricated using PBDTBT-DTBT (0.74 V) leading to a power conversion efficiency of 2.05% under AM 1.5G 100 mW/cm² illumination.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.258-261
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• 2011

A ferroelectric $(Bi,La)_4Ti_3O_{12}$ (BLT) thin film fabricated by the pulsed-DC sputtering method was evaluated on a cell structure to check its compatibility to high density ferroelectric random access memory (FeRAM) devices. The BLT composition in the sputtering target was $Bi_{4.8}La_{1.0}Ti_{3.0}O_{12}$. Firstly, a BLT film was deposited on a buried Pt/$IrO_x$/Ir bottom electrode stack with W-plug connected to the transistor in a lower place. Then, the film was finally crystallized at $700^{\circ}C$ for 30 seconds in oxygen ambient. The annealed BLT layer was found to have randomly oriented and small ellipsoidal-shaped grains (long direction: ~100 nm, short direction: ~20 nm). The small and uniform-sized grains with random orientations were considered to be suitable for high density FeRAM devices.