• Journal of Information Display
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• v.1 no.1
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• pp.3-8
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• 2000

We have developed a high performance vertical alignment TFT-LCD (Thin Film Transistor Liquid Crystal Display), that shows a high light transmittance, and wide viewing angle characteristics with an unusually high contrast ratio. In order to optimize the electro-optical properties we have studied the effect of cell parameters, multi-domain structure and retardation film compensation. With the optimized cell parameters and process conditions, we have achieved a 24" wide UXGA TFTLCD monitor (16:10 aspect ratio 1920X1200) showing a contrast ratio of over 500:1, panel transmittance near 4.5%, response time near 25 ms, and viewing angle higher than 80 degree in all directions.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.561-562
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• 2006

This paper presents an SRAM which uses the technique to equalize the internal cell node by adding an NMOS transistor. Accordingly, the write driver operates rapidly in a differential current of bit lines, and the operation speed of SRAM improves. An SRAM was implemented with a memory cell, a sense amplifier and a write driver. The SRAM obtained the performance of 18% power reduction and improvement of 56% operation speed. And Power delay product was reduced with 63%. The proposed SRAM was designed based on a 0.35um 1P4M CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.277-277
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• 2012

PCDTBT (Poly[N-9''-hepta-decanyl-2,7-carbazole-alt-5,5-(4',7'-di-2-thienyl-2',1',3'-benzothiadiazole)]) is an attractive material as a semiconducting polymer for organic thin film transistor (OTFT) and organic solar cell (OSC). High power conversion efficiency (~6%) under simulated AM 1.5G solar illumination of bulk-heterojunction solar cell with PCDTBT and [6,6]-phenyl C60 butyric acid methyl ester (PC61BM) blend was reported. In OSC, it is known that the band alignment at the interface between donor and acceptor is critical. Therefore, we studied the interfacial electronic structures of PCDTBT and PC61BM. The polymers are deposited by electro-spray on gold and In-situ x-ray and ultraviolet photoelectron spectroscopy measurements revealed the interfacial electronic structures. We obtained the energy level alignment between two materials and the different interface formation was observed with different deposition order.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.