• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Journal of Power Electronics
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• 제16권4호
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• pp.1415-1425
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• 2016

This paper presents a new approach for fault diagnosis in three-level neutral point clamped inverters. The proposed method is based on the average values of the positive and negative parts of normalized output currents. This method is capable of detecting and locating multiple open-circuit faults in the controlled power switches of converters in half of a fundamental period of those currents. The implementation of this diagnostic approach only requires two output currents of the inverter. Therefore, no additional sensors are needed other than the ones already used by the control system of a drive based on this type of converter. Moreover, through the normalization of currents, the diagnosis is independent of the load level of the converter. The performance and effectiveness of the proposed diagnostic technique are validated by experimental results obtained under steady-state and transient conditions.

• 전력전자학회논문지
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• 제11권3호
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• pp.209-215
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• 2006

본 논문에서는 전압원 인버터의 출력전압 파형을 개선하여 PWM방식을 사용할 수 없는 중 대용량급 모터드라이버 및 UPS, STATCOM, SVC등에 적용하기 위한 새로운 3상 전압원 24-스텝 인버터를 제안한다 보조회로로서 사용한 컨버터로 리플전압을 발생시키고 이를 기존의 12-스텝 인버터에 주입하는데 한대의 링크를 사용하면 12-스텝 동작이 24-스텝으로 전환되며 보조 변압기의 1차 권선을 2N(N=1,2,3...)으로 늘리면 12M-스텝(M=2,3,4..)으로 전환된다. 본 방식의 타당성을 실험 및 시뮬레이션을 통하여 입증하였다.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• 전력전자학회논문지
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• 제4권6호
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• pp.547-553
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• 1999

본 논문에서는 기존의 12-스텝 인버터에 간단한 보조회로를 추가하여 24-스텝(또는 36-스텝)의 출력파형을 갖는 새로운 방식의 이중접속 멀티스텝 인버터를 제안한다. 제안한 인버터의 보조회로는 두 개의 전압분할용 커패시터, 두 개의 스위칭소자와 저용량의 단권변압기로 구성된다. 이 보조회로의 동작으로 24-스텝의 입·출력 파형을 얻을 수 있으며 한 개의 양방향 스위칭 소자를 추가하면 36-스텝의 파형을 얻게된다. 스위칭 함수를 이용한 전압 및 전류의 분석을 통하여 설계에 필요한 최적의 파라미터를 설정하였다. 제안한 인버터는 PWM방식을 사용할 수 없는 중용량의 SVC등에 적용하면 효과적이다. 본 방식의 타당성을 실험 및 시뮬레이션을 통하여 입증하였다.

• 전력전자학회논문지
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• 제14권4호
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• pp.333-342
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• 2009

중성점 클램핑 방식(Neutral Point Clamped) 인버터로 알려져 있는 3레벨 NPC 인버터는 그 구조적 특성상 직류-링크(DC-link) 중성점(Neutral Point)에서 전압이 변동한다. 지금까지 많은 논문에서 이 문제에 대한 연구가 진행되었고 다양한 형태의 해결책들이 제시되었다. 그러나 인버터 내부에서 고장이 발생하여 그에 따른 고장허용제어가 NPC 인버터 시스템에 적용되었을 경우 중성점 전압변동은 정상 운전 시 나타나는 전압변동과 다르게 나타나기 때문에 고장허용 제어에 따른 중성점 전압변동에 대한 분석이 필요하다. 본 논문에서는 삼각파 비교 변조방법을 시스템에 적용하였을 경우 정상운전과 고장 발생 과 고장허용 제어 적용 시 직류-링크 중성점 전압 변동이 어떤 양상으로 나타나는지 분석하고 고장허용 제어에 의한 NPC 인버터의 고장검출 시간과 커패시터의 용량 사이의 관계를 고찰하였다. 시뮬레이션과 실험 결과를 이용하여 이론적 분석의 타당성을 검증하였다.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1519-1528
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• 2017

The paper proposes a well structured, component count waned single phase multilevel inverter (MLI) topology, which drives three different modules viz. Stipulation Based Sources Insertion (SBSI) module, Level Count Increasing (LCI) module and Inter-Linking H-Bridge (ILHB) module. The SBSI module confronts the number of basic sources needed in series/parallel to achieve required magnitude for any particular level. The LCI possesses an offsetting dc source and opuses to increase the number of levels and the ILHB module links the SBSI and LCI modules. A developed Hybrid Pulse Width Modulation (HPWM) strategy has PWM pulses for the switches of LCI module while the switches of the remaining two modules function at fundamental switching frequency. A fifteen level version of the proposed stipulation based sources insertion MLI (SBSIMLI) topology is simulated in MATLAB R2010a and a prototype of the similar specifications is constructed to validate the performance by experimental results. The comparison between the developed SBSIMLI topology and the competent topologies shows many interesting facts.

• Journal of Power Electronics
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• 제17권4호
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• pp.1037-1047
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• 2017

The Differential Power Processing (DPP) converter is a promising multi-module photovoltaic inverter architecture recently proposed for photovoltaic systems. In this paper, a DPP converter architecture, in which each PV-panel has its own DPP converter in shunt, performs distributed maximum power point tracking (DMPPT) control. It maintains a high energy conversion efficiency, even under partial shading conditions. The system architecture only deals with the power differences among the PV panels, which reduces the power capacity of the converters. Therefore, the DPP systems can easily overcome the conventional disadvantages of PCS such as centralized, string, and module integrated converter (MIC) topologies. Among the various types of the DPP systems, the feed-forward method has been selected for both its voltage balancing and power transfer to a modified H-bridge inverter that needs charge balancing of the input capacitors. The modified H-bridge multi-level inverter had some advantages such as a low part count and cost competitiveness when compared to conventional multi-level inverters. Therefore, it is frequently used in photovoltaic (PV) power conditioning system (PCS). However, its simplified switching network draws input current asymmetrically. Therefore, input capacitors in series suffer from a problem due to a charge imbalance. This paper validates the operating principle and feasibility of the proposed topology through the simulation and experimental results. They show that the input-capacitor voltages maintain the voltage balance with the PV MPPT control operating with a 140-W hardware prototype.

• 한국정밀공학회지
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• 제27권4호
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• pp.14-19
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• 2010

In this paper, using interleaved power factor correction how to improve the inverter efficiency studied. Interleaved method can reduce the conduction losses and the inductor energy. Generally, critical conduction mode (CRM) boost PFC converter used low power level because of the high peak currents. if you use the interleaved mode, CRM PFC can be used medium or high power application. interleaved CRM PFC can reduce current ripple for higher system reliability and size of buck capacitor and EMI filter size. Interleaved CRM PFC that is installed in front of inverter can maintain the constant voltage regardless of the input voltage.

• Journal of Power Electronics
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• 제16권4호
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.